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[/] [System11/] [trunk/] [rtl/] [vhdl/] [testbench3.vhd] - Diff between revs 2 and 4
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Rev 4 |
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity my_testbench is
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entity my_testbench3 is
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end my_testbench;
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end my_testbench3;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-- Architecture for CPU11 Testbench 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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architecture behavior of my_testbench3 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal uart_irq : Std_Logic;
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signal uart_irq : Std_Logic;
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signal timer_irq : std_logic;
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signal timer_irq : std_logic;
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