URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [bus/] [test_pins.sv] - Diff between revs 3 and 8
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 3 |
Rev 8 |
Line 98... |
Line 98... |
// Instantiate bus block and assign identical nets and variables
|
// Instantiate bus block and assign identical nets and variables
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
|
|
address_pins address_pins_inst( .*, .bus_ab_pin_we(ctl_ab_we), .address(ab[15:0]), .abus(apin[15:0]) );
|
address_pins address_pins_inst( .*, .bus_ab_pin_we(ctl_ab_we), .address(ab[15:0]), .abus(apin[15:0]) );
|
|
|
data_pins data_pins_inst( .*, .bus_db_oe(ctl_db_pin_oe), .ctl_bus_db_we(ctl_db_we), .bus_db_pin_oe(ctl_db_pin_oe), .bus_db_pin_re(ctl_db_pin_re), .D(dpin[7:0]) );
|
data_pins data_pins_inst( .*, .ctl_bus_db_oe(ctl_db_pin_oe), .ctl_bus_db_we(ctl_db_we), .bus_db_pin_oe(ctl_db_pin_oe), .bus_db_pin_re(ctl_db_pin_re), .D(dpin[7:0]) );
|
|
|
endmodule
|
endmodule
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.