URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [control/] [exec_zero.vh] - Diff between revs 6 and 8
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 6 |
Rev 8 |
Line 72... |
Line 72... |
ctl_flags_hf_cpl = 0;
|
ctl_flags_hf_cpl = 0;
|
ctl_flags_use_cf2 = 0;
|
ctl_flags_use_cf2 = 0;
|
ctl_flags_hf2_we = 0;
|
ctl_flags_hf2_we = 0;
|
ctl_flags_nf_clr = 0;
|
ctl_flags_nf_clr = 0;
|
ctl_alu_zero_16bit = 0;
|
ctl_alu_zero_16bit = 0;
|
ctl_flags_cf2_sel = 0;
|
ctl_flags_cf2_sel_shift = 0;
|
|
ctl_flags_cf2_sel_daa = 0;
|
|
|
// Module: registers/reg_file.v
|
// Module: registers/reg_file.v
|
ctl_sw_4d = 0;
|
|
ctl_sw_4u = 0;
|
ctl_sw_4u = 0;
|
ctl_reg_in_hi = 0;
|
ctl_reg_in_hi = 0;
|
ctl_reg_in_lo = 0;
|
ctl_reg_in_lo = 0;
|
ctl_reg_out_lo = 0;
|
ctl_reg_out_lo = 0;
|
ctl_reg_out_hi = 0;
|
ctl_reg_out_hi = 0;
|
Line 95... |
Line 95... |
ctl_reg_gp_we = 0;
|
ctl_reg_gp_we = 0;
|
ctl_reg_not_pc = 0;
|
ctl_reg_not_pc = 0;
|
ctl_reg_sys_we_lo = 0;
|
ctl_reg_sys_we_lo = 0;
|
ctl_reg_sys_we_hi = 0;
|
ctl_reg_sys_we_hi = 0;
|
ctl_reg_sys_we = 0;
|
ctl_reg_sys_we = 0;
|
|
ctl_sw_4d = 0;
|
ctl_reg_gp_hilo = 0;
|
ctl_reg_gp_hilo = 0;
|
ctl_reg_gp_sel = 0;
|
ctl_reg_gp_sel = 0;
|
ctl_reg_sys_hilo = 0;
|
ctl_reg_sys_hilo = 0;
|
|
|
// Module: bus/address_latch.v
|
// Module: bus/address_latch.v
|
ctl_inc_cy = 0;
|
ctl_inc_cy = 0;
|
ctl_inc_dec = 0;
|
ctl_inc_dec = 0;
|
ctl_inc_zero = 0;
|
|
ctl_al_we = 0;
|
ctl_al_we = 0;
|
ctl_inc_limit6 = 0;
|
ctl_inc_limit6 = 0;
|
ctl_bus_inc_oe = 0;
|
ctl_bus_inc_oe = 0;
|
ctl_apin_mux = 0;
|
ctl_apin_mux = 0;
|
ctl_apin_mux2 = 0;
|
ctl_apin_mux2 = 0;
|
|
|
// Module: bus/bus_control.v
|
// Module: bus/bus_control.v
|
ctl_bus_ff_oe = 0;
|
ctl_bus_ff_oe = 0;
|
ctl_bus_zero_oe = 0;
|
ctl_bus_zero_oe = 0;
|
ctl_bus_db_oe = 0;
|
|
|
|
// Module: bus/bus_switch.sv
|
// Module: bus/bus_switch.v
|
ctl_sw_1u = 0;
|
ctl_sw_1u = 0;
|
ctl_sw_1d = 0;
|
ctl_sw_1d = 0;
|
ctl_sw_2u = 0;
|
ctl_sw_2u = 0;
|
ctl_sw_2d = 0;
|
ctl_sw_2d = 0;
|
ctl_sw_mask543_en = 0;
|
ctl_sw_mask543_en = 0;
|
|
|
// Module: bus/data_pins.v
|
// Module: bus/data_pins.v
|
ctl_bus_db_we = 0;
|
ctl_bus_db_we = 0;
|
|
ctl_bus_db_oe = 0;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.