Line 23... |
Line 23... |
files = f.read().splitlines()
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files = f.read().splitlines()
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# Create 2 files that should be included in the execution engine block:
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# Create 2 files that should be included in the execution engine block:
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# 1. A module arguments section
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# 1. A module arguments section
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# 2. A file containing the code to initialize control wires to zero
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# 2. A file containing the code to initialize control wires to zero
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with open('exec_module.i', 'w') as file1, open('exec_zero.i', 'w') as file0:
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with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
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file1.write("// Automatically generated by genref.py\n")
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file1.write("// Automatically generated by genref.py\n")
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file0.write("// Automatically generated by genref.py\n")
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file0.write("// Automatically generated by genref.py\n")
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|
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# Read and parse each file from the list of input files
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# Read and parse each file from the list of input files
|
for infile in files:
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for infile in files:
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Line 43... |
Line 43... |
# input wire [1:0] bus case
|
# input wire [1:0] bus case
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if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
|
if len(info)>3 and info[0]=="input" and info[1]=="wire" and info[2].startswith("[") and info[3].startswith("ctl_"):
|
wires.append(info[2] + " " + info[3].translate(None, ';,'))
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wires.append(info[2] + " " + info[3].translate(None, ';,'))
|
|
|
if len(wires)>0:
|
if len(wires)>0:
|
with open('exec_module.i', 'a') as file1, open('exec_zero.i', 'a') as file0:
|
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
|
print "MODULE: " + infile
|
print "MODULE: " + infile
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file0.write("\n// Module: " + infile + "\n")
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file0.write("\n// Module: " + infile + "\n")
|
file1.write("\n// Module: " + infile + "\n")
|
file1.write("\n// Module: " + infile + "\n")
|
for wire in wires:
|
for wire in wires:
|
print " " + wire
|
print " " + wire
|
Line 57... |
Line 57... |
if "[" in wire:
|
if "[" in wire:
|
file0.write(wire.split()[1] + " = 0;\n")
|
file0.write(wire.split()[1] + " = 0;\n")
|
else:
|
else:
|
file0.write(wire + " = 0;\n")
|
file0.write(wire + " = 0;\n")
|
|
|
# Touch a file that includes 'exec_module.i' and 'exec_zero.i' to ensure it will recompile correctly
|
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
|
os.utime("execute.sv", None)
|
os.utime("execute.sv", None)
|
|
|
No newline at end of file
|
No newline at end of file
|