OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [control/] [memory_ifc.v] - Diff between revs 3 and 13

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 3 Rev 13
Line 12... Line 12... 
// Altera or its authorized distributors.  Please refer to the 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// applicable agreement for further details.
 
 
 
 
 
// PROGRAM              "Quartus II 64-Bit"
 
// PROGRAM              "Quartus II 64-Bit"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
 
// CREATED              "Sun Nov 16 21:11:14 2014"
 
// CREATED              "Sun Dec 04 01:04:33 2016"
 
 
 
 
 
module memory_ifc(
 
module memory_ifc(
 
        clk,
 
        clk,
 
        nM1_int,
 
        nM1_int,
 
        ctl_mRead,
 
        ctl_mRead,
Line 34... Line 34... 
        nRFSH_out,
 
        nRFSH_out,
 
        nMREQ_out,
 
        nMREQ_out,
 
        nRD_out,
 
        nRD_out,
 
        nWR_out,
 
        nWR_out,
 
        nIORQ_out,
 
        nIORQ_out,
 
        latch_wait
 
        latch_wait,
 
 
 
        wait_m1
 
);
 
);
 
 
 
 
 
 
 
 
 
input wire      clk;
 
input wire      clk;
 
input wire      nM1_int;
 
input wire      nM1_int;
Line 58... Line 59... 
output wire     nMREQ_out;
 
output wire     nMREQ_out;
 
output wire     nRD_out;
 
output wire     nRD_out;
 
output wire     nWR_out;
 
output wire     nWR_out;
 
output wire     nIORQ_out;
 
output wire     nIORQ_out;
 
output wire     latch_wait;
 
output wire     latch_wait;
 
 
 
output wire     wait_m1;
 
 
 
 
 
wire    intr_iorq;
 
wire    intr_iorq;
 
wire    ioRead;
 
wire    ioRead;
 
wire    iorq;
 
wire    iorq;
 
wire    ioWrite;
 
wire    ioWrite;
Line 72... Line 74... 
wire    nMEMRQ_int;
 
wire    nMEMRQ_int;
 
wire    nq2;
 
wire    nq2;
 
reg     q1;
 
reg     q1;
 
reg     q2;
 
reg     q2;
 
reg     wait_iorq;
 
reg     wait_iorq;
 
reg     wait_m1;
 
reg     wait_m_ALTERA_SYNTHESIZED1;
 
reg     wait_mrd;
 
reg     wait_mrd;
 
reg     wait_mwr;
 
reg     wait_mwr;
 
wire    SYNTHESIZED_WIRE_0;
 
wire    SYNTHESIZED_WIRE_0;
 
reg     DFFE_m1_ff3;
 
reg     DFFE_m1_ff3;
 
wire    SYNTHESIZED_WIRE_1;
 
wire    SYNTHESIZED_WIRE_1;
 
reg     SYNTHESIZED_WIRE_15;
 
 
 
reg     DFFE_iorq_ff4;
 
 
 
reg     SYNTHESIZED_WIRE_16;
 
reg     SYNTHESIZED_WIRE_16;
 
 
 
reg     DFFE_iorq_ff4;
 
 
 
reg     SYNTHESIZED_WIRE_17;
 
reg     DFFE_mrd_ff3;
 
reg     DFFE_mrd_ff3;
 
reg     DFFE_intr_ff3;
 
reg     DFFE_intr_ff3;
 
wire    SYNTHESIZED_WIRE_2;
 
wire    SYNTHESIZED_WIRE_2;
 
reg     SYNTHESIZED_WIRE_17;
 
 
 
reg     SYNTHESIZED_WIRE_18;
 
reg     SYNTHESIZED_WIRE_18;
 
wire    SYNTHESIZED_WIRE_19;
 
wire    SYNTHESIZED_WIRE_3;
 
wire    SYNTHESIZED_WIRE_4;
 
reg     SYNTHESIZED_WIRE_19;
 
 
 
wire    SYNTHESIZED_WIRE_20;
 
 
 
wire    SYNTHESIZED_WIRE_5;
 
reg     DFFE_iorq_ff1;
 
reg     DFFE_iorq_ff1;
 
reg     DFFE_m1_ff1;
 
reg     DFFE_m1_ff1;
 
reg     DFFE_mrd_ff1;
 
reg     DFFE_mrd_ff1;
 
reg     DFFE_mwr_ff1;
 
reg     DFFE_mwr_ff1;
 
reg     DFFE_mreq_ff2;
 
reg     DFFE_mreq_ff2;
 
 
 
 
 
assign  nM1_out = SYNTHESIZED_WIRE_18;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
assign  nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
 
assign  nMREQ_out = SYNTHESIZED_WIRE_0 & nMEMRQ_int;
 
 
 
 
 
assign  ioRead = iorq & fIORead;
 
assign  ioRead = iorq & fIORead;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m1);
 
assign  SYNTHESIZED_WIRE_1 = ~(DFFE_m1_ff3 | wait_m_ALTERA_SYNTHESIZED1);
 
 
 
 
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
assign  m1_mreq = ~(in_intr | SYNTHESIZED_WIRE_1);
 
 
 
 
 
assign  iorq = SYNTHESIZED_WIRE_15 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_16;
 
assign  iorq = SYNTHESIZED_WIRE_16 | DFFE_iorq_ff4 | SYNTHESIZED_WIRE_17;
 
 
 
 
 
assign  ioWrite = iorq & fIOWrite;
 
assign  ioWrite = iorq & fIOWrite;
 
 
 
 
 
assign  latch_wait = wait_mrd | wait_iorq | wait_m1 | wait_mwr;
 
assign  latch_wait = wait_mrd | wait_iorq | wait_m_ALTERA_SYNTHESIZED1 | wait_mwr;
 
 
 
 
 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
assign  nMEMRQ_int = ~(m1_mreq | mrd_mreq | mwr_mreq);
 
 
 
 
 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
 
assign  nRD_out = ~(m1_mreq | mrd_mreq | ioRead);
 
 
 
 
Line 124... Line 126... 
 
 
 
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
assign  mwr_mreq = mwr_wr | wait_mwr;
 
 
 
 
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
assign  nIORQ_out = ~(intr_iorq | iorq);
 
 
 
 
 
assign  SYNTHESIZED_WIRE_4 =  ~hold_clk_wait;
 
assign  SYNTHESIZED_WIRE_5 =  ~hold_clk_wait;
 
 
 
 
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
assign  intr_iorq = DFFE_intr_ff3 | wait_iorq;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_17);
 
assign  nM1_out = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_18;
 
 
 
 
 
 
 
assign  SYNTHESIZED_WIRE_0 = ~(SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_19);
 
 
 
 
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_18);
 
assign  nRFSH_out = ~(nq2 & SYNTHESIZED_WIRE_18);
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_iorq <= 0;
 
        wait_iorq <= 0;
 
        end
 
        end
Line 153... Line 157... 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_intr_ff3 <= 0;
 
        DFFE_intr_ff3 <= 0;
 
        end
 
        end
 
else
 
else
 
if (SYNTHESIZED_WIRE_4)
 
if (SYNTHESIZED_WIRE_5)
 
        begin
 
        begin
 
        DFFE_intr_ff3 <= wait_iorq;
 
        DFFE_intr_ff3 <= wait_iorq;
 
        end
 
        end
 
end
 
end
 
 
 
 
Line 178... Line 182... 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_16 <= 0;
 
        SYNTHESIZED_WIRE_17 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_16 <= DFFE_iorq_ff1;
 
        SYNTHESIZED_WIRE_17 <= DFFE_iorq_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_15 <= 0;
 
        SYNTHESIZED_WIRE_16 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_16;
 
        SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_17;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_iorq_ff4 <= 0;
 
        DFFE_iorq_ff4 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_15;
 
        DFFE_iorq_ff4 <= SYNTHESIZED_WIRE_16;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 230... Line 234... 
        SYNTHESIZED_WIRE_18 <= nM1_int;
 
        SYNTHESIZED_WIRE_18 <= nM1_int;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_m1_ff1 <= 1;
 
        DFFE_m1_ff1 <= 1;
 
        end
 
        end
Line 244... Line 248... 
        DFFE_m1_ff1 <= setM1;
 
        DFFE_m1_ff1 <= setM1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_m1 <= 0;
 
        wait_m_ALTERA_SYNTHESIZED1 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        wait_m1 <= DFFE_m1_ff1;
 
        wait_m_ALTERA_SYNTHESIZED1 <= DFFE_m1_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 267... Line 271... 
        DFFE_m1_ff3 <= 0;
 
        DFFE_m1_ff3 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_m1_ff3 <= wait_m1;
 
        DFFE_m1_ff3 <= wait_m_ALTERA_SYNTHESIZED1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 286... Line 290... 
        DFFE_mrd_ff1 <= ctl_mRead;
 
        DFFE_mrd_ff1 <= ctl_mRead;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_mrd <= 0;
 
        wait_mrd <= 0;
 
        end
 
        end
Line 300... Line 304... 
        wait_mrd <= DFFE_mrd_ff1;
 
        wait_mrd <= DFFE_mrd_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_mrd_ff3 <= 0;
 
        DFFE_mrd_ff3 <= 0;
 
        end
 
        end
Line 314... Line 318... 
        DFFE_mrd_ff3 <= wait_mrd;
 
        DFFE_mrd_ff3 <= wait_mrd;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_17 <= 0;
 
        SYNTHESIZED_WIRE_19 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_18;
 
        SYNTHESIZED_WIRE_19 <= SYNTHESIZED_WIRE_18;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        DFFE_mreq_ff2 <= 0;
 
        DFFE_mreq_ff2 <= 0;
 
        end
 
        end
 
else
 
else
 
if (timings_en)
 
if (timings_en)
 
        begin
 
        begin
 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_17;
 
        DFFE_mreq_ff2 <= SYNTHESIZED_WIRE_19;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
Line 356... Line 360... 
        DFFE_mwr_ff1 <= ctl_mWrite;
 
        DFFE_mwr_ff1 <= ctl_mWrite;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        wait_mwr <= 0;
 
        wait_mwr <= 0;
 
        end
 
        end
Line 370... Line 374... 
        wait_mwr <= DFFE_mwr_ff1;
 
        wait_mwr <= DFFE_mwr_ff1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
 
 
always@(posedge SYNTHESIZED_WIRE_19 or negedge nreset)
 
always@(posedge SYNTHESIZED_WIRE_20 or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
 
        begin
 
        begin
 
        mwr_wr <= 0;
 
        mwr_wr <= 0;
 
        end
 
        end
Line 383... Line 387... 
        begin
 
        begin
 
        mwr_wr <= wait_mwr;
 
        mwr_wr <= wait_mwr;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
assign  SYNTHESIZED_WIRE_19 =  ~clk;
 
assign  SYNTHESIZED_WIRE_20 =  ~clk;
 
 
 
 
 
assign  nq2 =  ~q2;
 
assign  nq2 =  ~q2;
 
 
 
 
 
assign  SYNTHESIZED_WIRE_2 =  ~DFFE_mreq_ff2;
 
assign  SYNTHESIZED_WIRE_2 =  ~nreset;
 
 
 
 
 
 
 
assign  SYNTHESIZED_WIRE_3 =  ~DFFE_mreq_ff2;
 
 
 
 
 
 
 
 
 
always@(posedge clk or negedge nreset)
 
always@(posedge clk or negedge nreset)
 
begin
 
begin
 
if (!nreset)
 
if (!nreset)
Line 417... Line 423... 
        begin
 
        begin
 
        q2 <= q1;
 
        q2 <= q1;
 
        end
 
        end
 
end
 
end
 
 
 
 
 
 
 
assign  wait_m1 = wait_m_ALTERA_SYNTHESIZED1;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.