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[/] [a-z80/] [trunk/] [cpu/] [control/] [test_sequencer.sv] - Diff between revs 3 and 8

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Rev 3 Rev 8
Line 19... Line 19...
logic hold_clk_iorq_sig=0;
logic hold_clk_iorq_sig=0;
logic hold_clk_wait_sig=0;
logic hold_clk_wait_sig=0;
logic hold_clk_busrq_sig=0;
logic hold_clk_busrq_sig=0;
 
 
wire T6_sig;
wire T6_sig;
wire M6_sig;
wire M5_sig;
assign nextM_sig = T6_sig;      // Restart when reaching T6
assign nextM_sig = T6_sig;      // Restart when reaching T6
assign setM1_sig = M6_sig;      // Restart when reaching M6
assign setM1_sig = M5_sig & T6_sig;     // Restart when reaching M5/T6
 
 
// ----------------- TEST -------------------
// ----------------- TEST -------------------
initial begin
initial begin
    // Init / reset
    // Init / reset
    `T  nreset = 1;
    `T  nreset = 1;
Line 52... Line 52...
    .M1(M1_sig) ,                       // output  M1_sig
    .M1(M1_sig) ,                       // output  M1_sig
    .M2(M2_sig) ,                       // output  M2_sig
    .M2(M2_sig) ,                       // output  M2_sig
    .M3(M3_sig) ,                       // output  M3_sig
    .M3(M3_sig) ,                       // output  M3_sig
    .M4(M4_sig) ,                       // output  M4_sig
    .M4(M4_sig) ,                       // output  M4_sig
    .M5(M5_sig) ,                       // output  M5_sig
    .M5(M5_sig) ,                       // output  M5_sig
    .M6(M6_sig) ,                       // output  M6_sig
 
    .T1(T1_sig) ,                       // output  T1_sig
    .T1(T1_sig) ,                       // output  T1_sig
    .T2(T2_sig) ,                       // output  T2_sig
    .T2(T2_sig) ,                       // output  T2_sig
    .T3(T3_sig) ,                       // output  T3_sig
    .T3(T3_sig) ,                       // output  T3_sig
    .T4(T4_sig) ,                       // output  T4_sig
    .T4(T4_sig) ,                       // output  T4_sig
    .T5(T5_sig) ,                       // output  T5_sig
    .T5(T5_sig) ,                       // output  T5_sig

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