Line 1... |
Line 1... |
#!/usr/bin/env python3
|
#!/usr/bin/env python3
|
#
|
#
|
# This script exports all core A-Z80 Verilog files to a destination of your choice.
|
# This script exports all core A-Z80 Verilog files to a destination folder of your choice.
|
# The files copied are necessary and sufficient to include with your custom project.
|
# Add all Verilog files (*.v) to your project and ensure that Verilog include files (*.vh)
|
|
# are on the include path.
|
#
|
#
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
# Copyright (C) 2014, 2016 Goran Devic, www.baltazarstudios.com
|
# Copyright (C) 2014,2017 Goran Devic, www.baltazarstudios.com
|
#
|
#
|
# This program is free software; you can redistribute it and/or modify it
|
# This program is free software; you can redistribute it and/or modify it
|
# under the terms of the GNU General Public License as published by the Free
|
# under the terms of the GNU General Public License as published by the Free
|
# Software Foundation; either version 2 of the License, or (at your option)
|
# Software Foundation; either version 2 of the License, or (at your option)
|
# any later version.
|
# any later version.
|
Line 20... |
Line 21... |
import os
|
import os
|
from shutil import copyfile
|
from shutil import copyfile
|
|
|
if len(sys.argv) != 2:
|
if len(sys.argv) != 2:
|
print ("\nUsage: export.py <destination-folder>\n")
|
print ("\nUsage: export.py <destination-folder>\n")
|
print ("Copies all core A-Z80 Verilog files to a destination of your choice.")
|
print ("Copies all core A-Z80 Verilog files to a destination folder of your choice.")
|
print ("The files copied are necessary and sufficient to include with your project.\n")
|
|
print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
|
|
print ("copy and use data_pins_lattice.v file instead.")
|
|
exit(-1)
|
exit(-1)
|
|
|
dest = sys.argv[1]
|
dest = sys.argv[1]
|
total = 0
|
total = 0
|
|
|
Line 53... |
Line 51... |
files = int(infile[6:])
|
files = int(infile[6:])
|
if total != files:
|
if total != files:
|
print ("ERROR: Incorrect number of files copied!")
|
print ("ERROR: Incorrect number of files copied!")
|
exit(-1)
|
exit(-1)
|
else:
|
else:
|
print ("\nDone copying {0} files.".format(files))
|
print ("\nDone copying {0} files.\n".format(files))
|
if not os.path.isfile(infile):
|
if not os.path.isfile(infile):
|
continue
|
continue
|
name = os.path.basename(infile)
|
name = os.path.basename(infile)
|
print ('Copying', infile)
|
print ('Copying', infile)
|
with open(dest + '/' + name, 'wt') as f:
|
with open(dest + '/' + name, 'wt') as f:
|
f.write(copyleft)
|
f.write(copyleft)
|
with open(infile) as g:
|
with open(infile) as g:
|
f.write(g.read())
|
f.write(g.read())
|
total += 1
|
total += 1
|
|
|
No newline at end of file
|
No newline at end of file
|
|
print ("All necessary A-Z80 CPU files are copied to", dest)
|
|
print ("Add all Verilog files (*.v) to your project and ensure that Verilog include")
|
|
print ("files (*.vh) are on the include path.\n")
|
|
print ("Use z80_top_direct_n.v as your top-level interface file.\n")
|
|
print ("Note for the users of Lattice FPGA toolset: instead of data_pins.v, manually")
|
|
print ("copy and use data_pins_lattice.v file instead.")
|
|
|
No newline at end of file
|
No newline at end of file
|