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//============================================================================
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//============================================================================
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// Include a list of top-level signal wires
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// Include a list of top-level signal wires
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`include "globals.vh"
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`include "globals.vh"
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// Specific to Modelsim, some modules in the schematics need to be pre-initialized
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// Specific to simulation, some modules in the schematics need to be pre-initialized
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// to avoid starting simulations with unknown values in selected flip flops.
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// to avoid starting simulations with unknown values in selected flip flops.
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// When synthesized, the CPU RESET input signal will do the work.
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reg fpga_reset = 1;
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reg fpga_reset = 0;
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always @(posedge clk)
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initial begin
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begin
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fpga_reset = 1;
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fpga_reset <= 0;
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#1 fpga_reset = 0;
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end
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end
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// Define internal data bus partitions separated by data bus switches
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// Define internal data bus partitions segmented by data bus switches
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wire [7:0] db0; // Segment connecting data pins and IR
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wire [7:0] db0; // Segment connecting data pins and IR
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wire [7:0] db1; // Segment with ALU
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wire [7:0] db1; // Segment leading to the ALU
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wire [7:0] db2; // Segment with msb part of the register address-side interface
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wire [7:0] db2; // Segment with msb part of the register address-side interface
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire [7:0] db_hi_as; // Register file data bus segment high byte
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// Control block
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wire [7:0] db_lo_as; // Register file data bus segment low byte
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Collect the PLA instruction decode prefix bitfield
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wire [6:0] prefix; // Instruction decode PLA prefix bitfield
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logic [6:0] prefix;
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assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
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assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
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ir instruction_reg_( .*, .db(db0[7:0]) );
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wire nM1_int; // External pins timing control
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pla_decode pla_decode_( .* );
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assign nM1_int = !(setM1 | (fFetch & T1));
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resets reset_block_( .* );
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sequencer sequencer_( .* );
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`include "coremodules.vh"
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execute execute_( .* );
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interrupts interrupts_( .*, .db(db0[4:3]) );
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decode_state decode_state_( .* );
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clk_delay clk_delay_( .* );
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pin_control pin_control_( .* );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// ALU and ALU control, including the flags
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
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alu_select alu_select_( .* );
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alu_flags alu_flags_( .*, .db(db1[7:0]) );
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alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Register file and register control
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire [7:0] db_hi_as;
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wire [7:0] db_lo_as;
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reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
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reg_control reg_control_( .* );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Address latch (with the incrementer)
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Timing control of the external pins
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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wire nM1_int;
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assign nM1_int = !((setM1 & nextM) | (fFetch & T1));
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memory_ifc memory_ifc_( .* );
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// Data path within the CPU in various forms, ending with data pins
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// Data path within the CPU in various forms, ending with data pins
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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bus_switch bus_switch_( .* );
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data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
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data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
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// Controls writers to the first section of the data bus
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bus_control bus_control_( .*, .db(db0[7:0]) );
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// Data switch SW1 with the data mask
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// Data switch SW1 with the data mask
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data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
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data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
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No newline at end of file
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No newline at end of file
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/* This SystemVerilog-style code is kept for future reference
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// Control block
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clk_delay clk_delay_( .* );
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decode_state decode_state_( .* );
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execute execute_( .* );
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interrupts interrupts_( .*, .db(db0[4:3]) );
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ir ir_( .*, .db(db0[7:0]) );
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pin_control pin_control_( .* );
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pla_decode pla_decode_( .* );
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resets resets_( .* );
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sequencer sequencer_( .* );
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// ALU and ALU control, including the flags
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alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
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alu_select alu_select_( .* );
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alu_flags alu_flags_( .*, .db(db1[7:0]) );
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alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
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// Register file and register control
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reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
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reg_control reg_control_( .* );
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// Address latch and the incrementer
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address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
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// Misc bus
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bus_control bus_control_( .*, .db(db0[7:0]) );
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bus_switch bus_switch_( .* );
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// Timing control of the external pins
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memory_ifc memory_ifc_( .* );
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*/
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No newline at end of file
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No newline at end of file
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