| Line 17... |
Line 17... |
# 3. You want to run a full Fuse test suite (all instructions!):
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# 3. You want to run a full Fuse test suite (all instructions!):
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# start_test = "00"
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# start_test = "00"
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# run_tests = -1
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# run_tests = -1
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# regress = 0
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# regress = 0
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#
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#
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# Orthogonal to that, set m1wait to a non-zero value to test nWAIT insertion at
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# the first M1 cycle of an instruction. Change it to the number of T-clocks to
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# insert.
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014 Goran Devic
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# Copyright (C) 2016 Goran Devic
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#
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#
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# This program is free software; you can redistribute it and/or modify it
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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# any later version.
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| Line 38... |
Line 42... |
start_test = "00"
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start_test = "00"
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# Number of tests to run; use -1 to run all tests
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# Number of tests to run; use -1 to run all tests
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run_tests = 1
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run_tests = 1
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# Set this to 1 to use regression test files instead of 'tests.*'
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# Set this to 1 to use regression test instead of selected or full 'tests.*'
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# It will run all regression tests (start_test, run_tests are ignored)
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# Regression test is a shorter set of tests and ignores start_test and run_tests values
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regress = 1
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regress = 1
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# Set this to a number of WAIT cycles to add at M1 clock period or 0 not to test nWAIT
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m1wait = 0
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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# Determine which test files to use
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# Determine which test files to use
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tests_in = 'fuse/tests.in'
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tests_in = 'fuse/tests.in'
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tests_expected = 'fuse/tests.expected'
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tests_expected = 'fuse/tests.expected'
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|
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| Line 98... |
Line 105... |
# Initial pre-test state is reset and control signals asserted
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# Initial pre-test state is reset and control signals asserted
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ftest.write("force dut.resets_.clrpc=0;\n")
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ftest.write("force dut.resets_.clrpc=0;\n")
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ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
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ftest.write("force dut.reg_file_.reg_gp_we=0;\n")
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ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
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ftest.write("force dut.reg_control_.ctl_reg_sys_we=0;\n")
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ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
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ftest.write("force dut.z80_top_ifc_n.fpga_reset=1;\n")
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ftest.write("#2\n")
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ftest.write("#2 // Start test loop\n\n")
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total_clks = total_clks + 2
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total_clks = total_clks + 2
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|
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# Read each test from the testdat.in file
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# Read each test from the testdat.in file
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while True:
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while True:
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ftest.write("//" + "-" * 80 + "\n")
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if len(t1)==0 or run_tests==0:
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if len(t1)==0 or run_tests==0:
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break
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break
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run_tests = run_tests-1
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run_tests = run_tests-1
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|
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# Clear opcode register before starting a new instruction
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# Clear opcode register before starting a new instruction
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| Line 188... |
Line 194... |
# it from writing to system registers so it cannot update PC and IR.
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# it from writing to system registers so it cannot update PC and IR.
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ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
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ftest.write(" force dut.z80_top_ifc_n.fpga_reset=0;\n")
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ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
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ftest.write(" force dut.address_latch_.Q=16'h" + r[11] +";\n") # Force PC into the address latch
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ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
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ftest.write(" release dut.reg_control_.ctl_reg_sys_we;\n")
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ftest.write(" release dut.reg_file_.reg_gp_we;\n")
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ftest.write(" release dut.reg_file_.reg_gp_we;\n")
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ftest.write("#3\n") # 1T (#2) overlaps the reset cycle
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ftest.write("#2 // Execute: M1/T1 start\n") # 1T (#2) overlaps the reset cycle
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ftest.write("#1 release dut.address_latch_.Q;\n")
|
total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
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total_clks = total_clks + 3 # We borrow 1T (#2) to to force the PC to be what our test wants...
|
ftest.write(" release dut.address_latch_.Q;\n")
|
|
ftest.write("#1\n")
|
ftest.write("#1\n")
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total_clks = total_clks + 1
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total_clks = total_clks + 1
|
|
|
# Read and parse the tests expected list which contains the expected results of our run,
|
# Read and parse the tests expected list which contains the expected results of our run,
|
# including the number of clocks for a particular instruction
|
# including the number of clocks for a particular instruction
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| Line 213... |
Line 219... |
s = t2.pop(0).split(' ')
|
s = t2.pop(0).split(' ')
|
s = list(filter(None, s))
|
s = list(filter(None, s))
|
|
|
ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
|
ticks = int(s[6]) * 2 - 2 # We return 1T (#2) that we borrowed to set PC
|
total_clks = total_clks + ticks
|
total_clks = total_clks + ticks
|
ftest.write("#" + str(ticks) + " // Execute\n")
|
|
|
# Test WAIT state insertion at the M1 clock cycle
|
|
if m1wait:
|
|
ftest.write(" z.nWAIT <= 0;\n")
|
|
ftest.write("#" + str(m1wait * 2) + " z.nWAIT <= 1; // nWAIT during M1\n")
|
|
total_clks = total_clks + m1wait * 2
|
|
|
|
ftest.write("#" + str(ticks) + " // Wait for opcode end\n")
|
|
|
ftest.write(" force dut.reg_control_.ctl_reg_sys_we=0;\n")
|
ftest.write(" force dut.reg_control_.ctl_reg_sys_we=0;\n")
|
ftest.write("#2 pc=z.A;\n") # Extra 2T for the next instruction overlap & read PC on the ABus
|
ftest.write("#2 pc=z.A;\n") # Extra 2T for the next instruction overlap & read PC on the ABus
|
ftest.write("#2\n") # Complete this instruction
|
ftest.write("#2\n") # Complete this instruction
|
ftest.write("#1 force dut.reg_file_.reg_gp_we=0;\n") # Add 1/2 clock for any pending flops to latch (mainly the F register)
|
ftest.write("#1 force dut.reg_file_.reg_gp_we=0;\n") # Add 1/2 clock for any pending flops to latch (mainly the F register)
|
| Line 276... |
Line 289... |
ftest.write(" if (ram.Mem[" + str(address) + "]!==8'h" + d + ") $fdisplay(f,\"* Mem[" + hex(address)[2:] + "]=%h !=" + d + "\",ram.Mem[" + str(address) + "]);\n")
|
ftest.write(" if (ram.Mem[" + str(address) + "]!==8'h" + d + ") $fdisplay(f,\"* Mem[" + hex(address)[2:] + "]=%h !=" + d + "\",ram.Mem[" + str(address) + "]);\n")
|
address = address+1
|
address = address+1
|
# Read a list of IO checks that was compiled while parsing the initial condition
|
# Read a list of IO checks that was compiled while parsing the initial condition
|
while len(check_io)>0:
|
while len(check_io)>0:
|
ftest.write(check_io.pop(0))
|
ftest.write(check_io.pop(0))
|
|
ftest.write("#1 // End opcode\n\n")
|
|
total_clks = total_clks + 1
|
|
|
# Write out the total number of clocks that this set of tests takes to execute
|
# Write out the total number of clocks that this set of tests takes to execute
|
ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n")
|
ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n")
|
ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n")
|
ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n")
|
|
ftest.close()
|
|
|
# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly
|
# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly
|
os.utime("test_fuse.sv", None)
|
os.utime("test_fuse.sv", None)
|
|
|
No newline at end of file
|
No newline at end of file
|
