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[/] [a-z80/] [trunk/] [cpu/] [toplevel/] [genglobals.py] - Diff between revs 6 and 8

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Rev 6 Rev 8
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#!/usr/bin/env python
#!/usr/bin/env python3
#
#
# This script reads and parses selected Verilog and SystemVerilog modules
# This script reads and parses selected Verilog and SystemVerilog modules
# and generates a set of Verilog include files for the Z80 top-level block.
# and generates a set of Verilog include files for the Z80 top-level block.
#
#
#-------------------------------------------------------------------------------
#-------------------------------------------------------------------------------
Line 34... Line 34...
    if not os.path.isfile('../' + infile):
    if not os.path.isfile('../' + infile):
        continue
        continue
    with open('../' + infile, "r") as f:
    with open('../' + infile, "r") as f:
        for line in f:
        for line in f:
            info = line.split()
            info = line.split()
            if (len(info)>2):
            if len(info)>2:
                # There can be only one driver for each signal so we read only the outputs
                # There can be only one driver for each signal so we read only the outputs
                if (info[0]=="output") and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
                if info[0]=="output" and (info[1]=="wire" or info[1]=="reg" or info[1]=="logic"):
                    # There are 2 cases: wires and buses
                    # There are 2 cases: wires and buses
                    if info[2].startswith('['):
                    if info[2].startswith('['):
                        wires.append(info[2] + ' ' + info[3].translate(None, ';,'))
                        wires.append(info[2] + ' ' + info[3].strip(';,'))
                    else:
                    else:
                        wires.append(info[2].translate(None, ';,'))
                        wires.append(info[2].strip(';,'))
 
 
    if len(wires)>0:
    if len(wires)>0:
        with open('globals.vh', 'a') as file1:
        with open('globals.vh', 'a') as file1:
            file1.write("\n// Module: " + infile + "\n")
            file1.write("\n// Module: " + infile + "\n")
            for wire in wires:
            for wire in wires:
Line 57... Line 57...
                    file1.write("wire " + wire + ";\n")
                    file1.write("wire " + wire + ";\n")
                    globals.append(wire)
                    globals.append(wire)
 
 
# Touch files that include 'globals.vh' to ensure it will recompile correctly
# Touch files that include 'globals.vh' to ensure it will recompile correctly
os.utime("core.vh", None)
os.utime("core.vh", None)
os.utime("z80_top_direct_n.sv", None)
os.utime("z80_top_direct_n.v", None)
os.utime("z80_top_ifc_n.sv", None)
os.utime("z80_top_ifc_n.sv", None)
 
 
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