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                           A-Z80
                           A-Z80
         A conceptual implementation of the Z80 CPU
         A conceptual implementation of the Z80 CPU
         ------------------------------------------
         ------------------------------------------
 
                    for Altera and Xilinx FPGAs
 
 
This project is described in more details at: www.baltazarstudios.com
This project is described in more details at: www.baltazarstudios.com
 
 
Prerequisites:
Prerequisites:
* Altera Quartus and Modelsim (free web editions)
* Altera Quartus and Modelsim (free web editions) OR
* Python 2.7
* Xilinx ISE (free Webpack edition)
 
* Python 3.5.x
 
 
A-Z80 "cpu" consists of several functional blocks and a top-level module:
A-Z80 "cpu" consists of several functional blocks and a top-level module:
  alu         contains ALU block, ALU control and flags logic
  alu         contains ALU block, ALU control and flags logic
  bus         contains data bus switches, pin logic, address latch and the
  bus         contains data bus switches, pin logic, address latch and the
              address incrementer
              address incrementer
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"host" integrates the A-Z80 into several complete top-level designs:
"host" integrates the A-Z80 into several complete top-level designs:
  "basic" contains a simplified board consisting of A-Z80 CPU, memory
  "basic" contains a simplified board consisting of A-Z80 CPU, memory
          and UART modules that can run small Z80 programs
          and UART modules that can run small Z80 programs
  "zxspectrum" contains an implementation of the Sinclair ZX Spectrum
  "zxspectrum" contains an implementation of the Sinclair ZX Spectrum
 
 
  You probably want to start by loading one of those two designs in Quartus.
  You probably want to start by loading one of those designs.
 
 
"tools" contains various tools related to the project.
"tools" contains various tools related to the project.
 
 
Read the 'readme.txt' files in each of the folders for additional information.
Read the 'readme.txt' files in each of the folders for additional information.
Read 'Quick Start' and 'Users Guide' documents in the 'docs' folder.
Read 'Quick Start' and 'Users Guide' documents in the 'docs' folder.
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==================
==================
Each functional block contains a Quartus project file:
Each functional block contains a Quartus project file:
.//test_.qpf
.//test_.qpf
 
 
Quartus projects are only used as containers for files within individual
Quartus projects are only used as containers for files within individual
modules; complete top-level solutions that use A-Z80 are in the "host" folder.
modules; complete and working top-level solutions that use A-Z80 are in the
 
"host" folder.
 
 
Majority of sub-modules are designed in the Quartus schematic editor and then
Majority of sub-modules are designed in the Quartus schematic editor and then
exported to Verilog for simulation and the top-level integration. If you decide
exported to Verilog for simulation and top-level integration. If you decide
to create a design using the A-Z80, you can either use schematic files as sources
to create a design using the A-Z80 CPU, you can either use schematic files
(in Altera Quartus) or corresponding Verilog sources.
(in Altera Quartus) or corresponding Verilog sources (for both Altera
 
and Xilinx tools).
 
 
Simulation
Simulation
==========
==========
*** IMPORTANT ***
 
Before you can load and simulate any module through Modelsim, you need to set up
Before you can load and simulate any module through Modelsim, you need to set up
the environment by running a Python script 'modelsim_setup.py'. It creates
the environment by running a Python script 'modelsim_setup.py'. The script creates
relative file path mapping to source files in all module project folders.
relative file path mapping to source files in all module project folders.
 
 
Each functional block, including the top level, contains a Modelsim simulation
Each functional block, including the top level, contains a Modelsim simulation
profile: .//simulation/modelsim/test_.mpf
profile: .//simulation/modelsim/test_.mpf
 
 
*** IMPORTANT ***
After opening a Modelsim session, create a library and compile sources:
The first time you open any ModelSim session by opening a *.mpf file, you need to
 
create a library:
 
ModelSim> vlib work
ModelSim> vlib work
After that, you can compile sources (Compile->Compile All) and run a simulation
Compile->Compile All
through one of defined configurations.
Run a simulation through one of the defined configurations.
 
 
If you get a message "Unable to compile", you forgot to run 'modelsim_setup.py'.
If you get a message "Unable to compile", you likely forgot to run 'modelsim_setup.py'.
Exit ModelSim; git revert its changes to ".mpf" file (since it has been rewritten
Exit ModelSim, git revert changes to ".mpf" file, delete "work" folder and run
using absolute paths); delete "work" folder, run 'modelsim_setup.py' and restart.
'modelsim_setup.py'. Rinse, repeat.
You will have to recreate the library ('vlib work') and recompile.
 
 
 
Each project also contains a set of predefined waveform scripts that you can
Each project contains a set of predefined waveform scripts which you can
load before running a simulation of a particular module or a test:
load before running a simulation:
.//simulation/modelsim/wave_.do
.//simulation/modelsim/wave_.do
 
 
Email me if you have any questions,
Email me if you have any questions,
Goran Devic
Goran Devic
gdevic@yahoo.com
gdevic@yahoo.com

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