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[/] [ac97/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 10 and 12

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Line 35... Line 35... 
////                                                             ////
 
////                                                             ////
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
 
 
 
 
//  CVS Log
 
//  CVS Log
 
//
 
//
 
//  $Id: test_bench_top.v,v 1.2 2002-03-05 04:44:04 rudi Exp $
 
//  $Id: test_bench_top.v,v 1.3 2002-03-11 03:21:12 rudi Exp $
 
//
 
//
 
//  $Date: 2002-03-05 04:44:04 $
 
//  $Date: 2002-03-11 03:21:12 $
 
//  $Revision: 1.2 $
 
//  $Revision: 1.3 $
 
//  $Author: rudi $
 
//  $Author: rudi $
 
//  $Locker:  $
 
//  $Locker:  $
 
//  $State: Exp $
 
//  $State: Exp $
 
//
 
//
 
// Change History:
 
// Change History:
 
//               $Log: not supported by cvs2svn $
 
//               $Log: not supported by cvs2svn $
 
 
 
//               Revision 1.2  2002/03/05 04:44:04  rudi
 
 
 
//
 
 
 
//               - Fixed the order of the thrash hold bits to match the spec.
 
 
 
//               - Many minor synthesis cleanup items ...
 
 
 
//
 
//               Revision 1.1  2002/02/13 08:22:32  rudi
 
//               Revision 1.1  2002/02/13 08:22:32  rudi
 
//
 
//
 
//               Added test bench for public release
 
//               Added test bench for public release
 
//
 
//
 
//
 
//
Line 137... Line 142... 
// Misc Variables
 
// Misc Variables
 
reg     [31:0]   data;
 
reg     [31:0]   data;
 
reg     [31:0]   data1;
 
reg     [31:0]   data1;
 
reg     [31:0]   data2;
 
reg     [31:0]   data2;
 
reg     [31:0]   tmp;
 
reg     [31:0]   tmp;
 
integer         size, frames, m;
 
integer         size, frames, m, p;
 
 
 
 
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
//
 
//
 
// Defines 
// Defines 
//
 
//
Line 246... Line 251... 
        oc5_ptr = 0;
 
        oc5_ptr = 0;
 
        ic0_ptr = 0;
 
        ic0_ptr = 0;
 
        ic1_ptr = 0;
 
        ic1_ptr = 0;
 
        ic2_ptr = 0;
 
        ic2_ptr = 0;
 
 
 
 
 
 
 
 
 
 
 
        oc0_th = 4;
 
 
 
        oc1_th = 4;
 
 
 
        oc2_th = 4;
 
 
 
        oc3_th = 4;
 
 
 
        oc4_th = 4;
 
 
 
        oc5_th = 4;
 
 
 
        ic0_th = 4;
 
 
 
        ic1_th = 4;
 
 
 
        ic2_th = 4;
 
 
 
 
 
 
 
 
 
 
 
`ifdef AC97_OUT_FIFO_DEPTH_8
 
 
 
        oc0_th = oc0_th * 2;
 
 
 
        oc1_th = oc1_th * 2;
 
 
 
        oc2_th = oc2_th * 2;
 
 
 
        oc3_th = oc3_th * 2;
 
 
 
        oc4_th = oc4_th * 2;
 
 
 
        oc5_th = oc5_th * 2;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef AC97_OUT_FIFO_DEPTH_16
 
 
 
        oc0_th = oc0_th * 4;
 
 
 
        oc1_th = oc1_th * 4;
 
 
 
        oc2_th = oc2_th * 4;
 
 
 
        oc3_th = oc3_th * 4;
 
 
 
        oc4_th = oc4_th * 4;
 
 
 
        oc5_th = oc5_th * 4;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef AC97_IN_FIFO_DEPTH_8
 
 
 
        ic0_th = ic0_th * 2;
 
 
 
        ic1_th = ic1_th * 2;
 
 
 
        ic2_th = ic2_th * 2;
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef AC97_IN_FIFO_DEPTH_16
 
 
 
        ic0_th = ic0_th * 4;
 
 
 
        ic1_th = ic1_th * 4;
 
 
 
        ic2_th = ic2_th * 4;
 
 
 
`endif
 
 
 
 
 
 
 
 
 
 
 
 
 
        repeat(48)      @(posedge clk);
 
        repeat(48)      @(posedge clk);
 
        rst = 1;
 
        rst = 1;
 
        repeat(48)      @(posedge clk);
 
        repeat(48)      @(posedge clk);
 
 
 
 
 
        // HERE IS WHERE THE TEST CASES GO ...
 
        // HERE IS WHERE THE TEST CASES GO ...
Line 756... Line 805... 
always @(posedge clk)
 
always @(posedge clk)
 
if(oc0_dma_en & dma_req[0])
 
if(oc0_dma_en & dma_req[0])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_wr4(`OC0, 4'hf, 0, oc0_mem[oc0_ptr+0],
 
 
 
                                        oc0_mem[oc0_ptr+1],
 
        for(p=0;p<oc0_th;p=p+1)
 
                                        oc0_mem[oc0_ptr+2],
 
                m0.wb_wr1(`OC0,4'hf, oc0_mem[oc0_ptr+p] );
 
                                        oc0_mem[oc0_ptr+3]);
 
        oc0_ptr = oc0_ptr + oc0_th;
 
        oc0_ptr = oc0_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[0] = 1;
 
        dma_ack[0] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[0] = 0;
 
        #1 dma_ack[0] = 0;
 
   end
 
   end
Line 773... Line 822... 
always @(posedge clk)
 
always @(posedge clk)
 
if(oc1_dma_en & dma_req[1])
 
if(oc1_dma_en & dma_req[1])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_wr4(`OC1, 4'hf, 0, oc1_mem[oc1_ptr+0],
 
        for(p=0;p<oc1_th;p=p+1)
 
                                        oc1_mem[oc1_ptr+1],
 
                m0.wb_wr1(`OC1,4'hf, oc1_mem[oc1_ptr+p] );
 
                                        oc1_mem[oc1_ptr+2],
 
        oc1_ptr = oc1_ptr + oc1_th;
 
                                        oc1_mem[oc1_ptr+3]);
 
 
 
        oc1_ptr = oc1_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[1] = 1;
 
        dma_ack[1] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[1] = 0;
 
        #1 dma_ack[1] = 0;
 
   end
 
   end
Line 789... Line 836... 
always @(posedge clk)
 
always @(posedge clk)
 
if(oc2_dma_en & dma_req[2])
 
if(oc2_dma_en & dma_req[2])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_wr4(`OC2, 4'hf, 0, oc2_mem[oc2_ptr+0],
 
        for(p=0;p<oc2_th;p=p+1)
 
                                        oc2_mem[oc2_ptr+1],
 
                m0.wb_wr1(`OC2,4'hf, oc2_mem[oc2_ptr+p] );
 
                                        oc2_mem[oc2_ptr+2],
 
        oc2_ptr = oc2_ptr + oc2_th;
 
                                        oc2_mem[oc2_ptr+3]);
 
 
 
        oc2_ptr = oc2_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[2] = 1;
 
        dma_ack[2] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[2] = 0;
 
        #1 dma_ack[2] = 0;
 
   end
 
   end
Line 805... Line 850... 
always @(posedge clk)
 
always @(posedge clk)
 
if(oc3_dma_en & dma_req[3])
 
if(oc3_dma_en & dma_req[3])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_wr4(`OC3, 4'hf, 0, oc3_mem[oc3_ptr+0],
 
        for(p=0;p<oc3_th;p=p+1)
 
                                        oc3_mem[oc3_ptr+1],
 
                m0.wb_wr1(`OC3,4'hf, oc3_mem[oc3_ptr+p] );
 
                                        oc3_mem[oc3_ptr+2],
 
        oc3_ptr = oc3_ptr + oc3_th;
 
                                        oc3_mem[oc3_ptr+3]);
 
 
 
        oc3_ptr = oc3_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[3] = 1;
 
        dma_ack[3] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[3] = 0;
 
        #1 dma_ack[3] = 0;
 
   end
 
   end
Line 821... Line 864... 
always @(posedge clk)
 
always @(posedge clk)
 
if(oc4_dma_en & dma_req[4])
 
if(oc4_dma_en & dma_req[4])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_wr4(`OC4, 4'hf, 0, oc4_mem[oc4_ptr+0],
 
        for(p=0;p<oc4_th;p=p+1)
 
                                        oc4_mem[oc4_ptr+1],
 
                m0.wb_wr1(`OC4,4'hf, oc4_mem[oc4_ptr+p] );
 
                                        oc4_mem[oc4_ptr+2],
 
        oc4_ptr = oc4_ptr + oc4_th;
 
                                        oc4_mem[oc4_ptr+3]);
 
 
 
        oc4_ptr = oc4_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[4] = 1;
 
        dma_ack[4] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[4] = 0;
 
        #1 dma_ack[4] = 0;
 
   end
 
   end
Line 837... Line 878... 
always @(posedge clk)
 
always @(posedge clk)
 
if(oc5_dma_en & dma_req[5])
 
if(oc5_dma_en & dma_req[5])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_wr4(`OC5, 4'hf, 0, oc5_mem[oc5_ptr+0],
 
        for(p=0;p<oc5_th;p=p+1)
 
                                        oc5_mem[oc5_ptr+1],
 
                m0.wb_wr1(`OC5,4'hf, oc5_mem[oc5_ptr+p] );
 
                                        oc5_mem[oc5_ptr+2],
 
        oc5_ptr = oc5_ptr + oc5_th;
 
                                        oc5_mem[oc5_ptr+3]);
 
 
 
        oc5_ptr = oc5_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[5] = 1;
 
        dma_ack[5] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[5] = 0;
 
        #1 dma_ack[5] = 0;
 
   end
 
   end
Line 853... Line 892... 
always @(posedge clk)
 
always @(posedge clk)
 
if(ic0_dma_en & dma_req[6])
 
if(ic0_dma_en & dma_req[6])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_rd4(`IC0, 4'hf, 0, ic0_mem[ic0_ptr+0],
 
        for(p=0;p<ic0_th;p=p+1)
 
                                        ic0_mem[ic0_ptr+1],
 
                m0.wb_rd1(`IC0,4'hf, ic0_mem[ic0_ptr+p] );
 
                                        ic0_mem[ic0_ptr+2],
 
        ic0_ptr = ic0_ptr + ic0_th;
 
                                        ic0_mem[ic0_ptr+3]);
 
 
 
        ic0_ptr = ic0_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[6] = 1;
 
        dma_ack[6] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[6] = 0;
 
        #1 dma_ack[6] = 0;
 
   end
 
   end
Line 869... Line 906... 
always @(posedge clk)
 
always @(posedge clk)
 
if(ic1_dma_en & dma_req[7])
 
if(ic1_dma_en & dma_req[7])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_rd4(`IC1, 4'hf, 0, ic1_mem[ic1_ptr+0],
 
        for(p=0;p<ic1_th;p=p+1)
 
                                        ic1_mem[ic1_ptr+1],
 
                m0.wb_rd1(`IC1,4'hf, ic1_mem[ic1_ptr+p] );
 
                                        ic1_mem[ic1_ptr+2],
 
        ic1_ptr = ic1_ptr + ic1_th;
 
                                        ic1_mem[ic1_ptr+3]);
 
 
 
        ic1_ptr = ic1_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[7] = 1;
 
        dma_ack[7] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[7] = 0;
 
        #1 dma_ack[7] = 0;
 
   end
 
   end
Line 885... Line 920... 
always @(posedge clk)
 
always @(posedge clk)
 
if(ic2_dma_en & dma_req[8])
 
if(ic2_dma_en & dma_req[8])
 
   begin
 
   begin
 
        while(wb_busy)  @(posedge clk);
 
        while(wb_busy)  @(posedge clk);
 
        wb_busy = 1;
 
        wb_busy = 1;
 
        m0.wb_rd4(`IC2, 4'hf, 0, ic2_mem[ic2_ptr+0],
 
        for(p=0;p<ic2_th;p=p+1)
 
                                        ic2_mem[ic2_ptr+1],
 
                m0.wb_rd1(`IC2,4'hf, ic2_mem[ic2_ptr+p] );
 
                                        ic2_mem[ic2_ptr+2],
 
        ic2_ptr = ic2_ptr + ic2_th;
 
                                        ic2_mem[ic2_ptr+3]);
 
 
 
        ic2_ptr = ic2_ptr + 4;
 
 
 
        wb_busy = 0;
 
        wb_busy = 0;
 
        dma_ack[8] = 1;
 
        dma_ack[8] = 1;
 
        @(posedge clk);
 
        @(posedge clk);
 
        #1 dma_ack[8] = 0;
 
        #1 dma_ack[8] = 0;
 
   end
 
   end

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