OpenCores

Rev 10	Rev 11
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: tests.v,v 1.2 2002-03-05 04:44:04 rudi Exp $`	`// $Id: tests.v,v 1.3 2002-03-05 04:54:08 rudi Exp $`
`//`	`//`
`// $Date: 2002-03-05 04:44:04 $`	`// $Date: 2002-03-05 04:54:08 $`
`// $Revision: 1.2 $`	`// $Revision: 1.3 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/03/05 04:44:04 rudi`
	`//`
	`// - Fixed the order of the thrash hold bits to match the spec.`
	`// - Many minor synthesis cleanup items ...`
	`//`
`// Revision 1.1 2002/02/13 08:22:32 rudi`	`// Revision 1.1 2002/02/13 08:22:32 rudi`
`//`	`//`
`// Added test bench for public release`	`// Added test bench for public release`
`//`	`//`
`//`	`//`
Line 910...	Line 915...
m0.wb_wr1(`INTM,4'hf, 32'hffff_fffc);	m0.wb_wr1(`INTM,4'hf, 32'hffff_fffc);

`case(th)`	`case(th)`
`0:`	`0:`
`begin`	`begin`
`$display("Interrupt thrash hold: 100%");`	`$display("Interrupt threshold: 100%");`
`// Thrash holds`
`oc0_th = 4; // 100% (4/4) Full Empty`	`oc0_th = 4; // 100% (4/4) Full Empty`
`oc1_th = 4;`	`oc1_th = 4;`
`oc2_th = 4;`	`oc2_th = 4;`
`oc3_th = 4;`	`oc3_th = 4;`
`oc4_th = 4;`	`oc4_th = 4;`
Line 929...	Line 933...
m0.wb_wr1(`ICC,4'hf, 32'h0033_3333);	m0.wb_wr1(`ICC,4'hf, 32'h0033_3333);
`end`	`end`

`1:`	`1:`
`begin`	`begin`
`$display("Interrupt thrash hold: 75%");`	`$display("Interrupt threshold: 75%");`
`// Thrash holds`
`oc0_th = 3; // 75% (3/4) Full Empty`	`oc0_th = 3; // 75% (3/4) Full Empty`
`oc1_th = 3;`	`oc1_th = 3;`
`oc2_th = 3;`	`oc2_th = 3;`
`oc3_th = 3;`	`oc3_th = 3;`
`oc4_th = 3;`	`oc4_th = 3;`
Line 948...	Line 951...
m0.wb_wr1(`ICC,4'hf, 32'h0023_2323);	m0.wb_wr1(`ICC,4'hf, 32'h0023_2323);
`end`	`end`

`2:`	`2:`
`begin`	`begin`
`$display("Interrupt thrash hold: 50%");`	`$display("Interrupt threshold: 50%");`
`// Thrash holds`
`oc0_th = 2; // 50% (1/2) Full/Empty`	`oc0_th = 2; // 50% (1/2) Full/Empty`
`oc1_th = 2;`	`oc1_th = 2;`
`oc2_th = 2;`	`oc2_th = 2;`
`oc3_th = 2;`	`oc3_th = 2;`
`oc4_th = 2;`	`oc4_th = 2;`
Line 967...	Line 969...
m0.wb_wr1(`ICC,4'hf, 32'h0013_1313);	m0.wb_wr1(`ICC,4'hf, 32'h0013_1313);
`end`	`end`

`3:`	`3:`
`begin`	`begin`
`$display("Interrupt thrash hold: 25%");`	`$display("Interrupt threshold: 25%");`
`// Thrash holds`
`oc0_th = 1; // 25% (1/4) Full/Empty`	`oc0_th = 1; // 25% (1/4) Full/Empty`
`oc1_th = 1;`	`oc1_th = 1;`
`oc2_th = 1;`	`oc2_th = 1;`
`oc3_th = 1;`	`oc3_th = 1;`
`oc4_th = 1;`	`oc4_th = 1;`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: tests.v,v 1.2 2002-03-05 04:44:04 rudi Exp $

//  $Id: tests.v,v 1.3 2002-03-05 04:54:08 rudi Exp $

//

//

//  $Date: 2002-03-05 04:44:04 $

//  $Date: 2002-03-05 04:54:08 $

//  $Revision: 1.2 $

//  $Revision: 1.3 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.2  2002/03/05 04:44:04  rudi

//

//               - Fixed the order of the thrash hold bits to match the spec.

//               - Many minor synthesis cleanup items ...

//

//               Revision 1.1  2002/02/13 08:22:32  rudi

//               Revision 1.1  2002/02/13 08:22:32  rudi

//

//

//               Added test bench for public release

//               Added test bench for public release

//

//

//

//

Line 910...

Line 915...

        m0.wb_wr1(`INTM,4'hf, 32'hffff_fffc);

        m0.wb_wr1(`INTM,4'hf, 32'hffff_fffc);

        case(th)

        case(th)

0:

0:

        begin

        begin

        $display("Interrupt thrash hold: 100%");

        $display("Interrupt threshold: 100%");

        // Thrash holds

        oc0_th = 4;     // 100% (4/4) Full Empty

        oc0_th = 4;     // 100% (4/4) Full Empty

        oc1_th = 4;

        oc1_th = 4;

        oc2_th = 4;

        oc2_th = 4;

        oc3_th = 4;

        oc3_th = 4;

        oc4_th = 4;

        oc4_th = 4;

Line 929...

Line 933...

        m0.wb_wr1(`ICC,4'hf, 32'h0033_3333);

        m0.wb_wr1(`ICC,4'hf, 32'h0033_3333);

end

end

1:

1:

        begin

        begin

        $display("Interrupt thrash hold: 75%");

        $display("Interrupt threshold: 75%");

        // Thrash holds

        oc0_th = 3;     // 75% (3/4) Full Empty

        oc0_th = 3;     // 75% (3/4) Full Empty

        oc1_th = 3;

        oc1_th = 3;

        oc2_th = 3;

        oc2_th = 3;

        oc3_th = 3;

        oc3_th = 3;

        oc4_th = 3;

        oc4_th = 3;

Line 948...

Line 951...

        m0.wb_wr1(`ICC,4'hf, 32'h0023_2323);

        m0.wb_wr1(`ICC,4'hf, 32'h0023_2323);

end

end

2:

2:

        begin

        begin

        $display("Interrupt thrash hold: 50%");

        $display("Interrupt threshold: 50%");

        // Thrash holds

        oc0_th = 2;     // 50% (1/2) Full/Empty

        oc0_th = 2;     // 50% (1/2) Full/Empty

        oc1_th = 2;

        oc1_th = 2;

        oc2_th = 2;

        oc2_th = 2;

        oc3_th = 2;

        oc3_th = 2;

        oc4_th = 2;

        oc4_th = 2;

Line 967...

Line 969...

        m0.wb_wr1(`ICC,4'hf, 32'h0013_1313);

        m0.wb_wr1(`ICC,4'hf, 32'h0013_1313);

end

end

3:

3:

        begin

        begin

        $display("Interrupt thrash hold: 25%");

        $display("Interrupt threshold: 25%");

        // Thrash holds

        oc0_th = 1;     // 25% (1/4) Full/Empty

        oc0_th = 1;     // 25% (1/4) Full/Empty

        oc1_th = 1;

        oc1_th = 1;

        oc2_th = 1;

        oc2_th = 1;

        oc3_th = 1;

        oc3_th = 1;

        oc4_th = 1;

        oc4_th = 1;

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