| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: tests.v,v 1.3 2002-03-05 04:54:08 rudi Exp $
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// $Id: tests.v,v 1.4 2002-03-11 03:21:12 rudi Exp $
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//
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//
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// $Date: 2002-03-05 04:54:08 $
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// $Date: 2002-03-11 03:21:12 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/03/05 04:54:08 rudi
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//
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// - fixed spelling
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//
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// Revision 1.2 2002/03/05 04:44:04 rudi
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// Revision 1.2 2002/03/05 04:44:04 rudi
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//
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//
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Many minor synthesis cleanup items ...
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// - Many minor synthesis cleanup items ...
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//
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//
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| Line 172... |
Line 176... |
error_cnt = error_cnt + 1;
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error_cnt = error_cnt + 1;
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end
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end
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end
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end
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size = frames - 4;
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size = frames - 12;
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for(n=0;n<size;n=n+1)
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for(n=0;n<size;n=n+1)
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begin
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begin
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data1 = u1.rs3_mem[n];
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data1 = u1.rs3_mem[n];
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data = oc0_mem[n[8:1]];
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data = oc0_mem[n[8:1]];
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| Line 984... |
Line 988... |
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m0.wb_wr1(`OCC0,4'hf, 32'h0303_0303);
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m0.wb_wr1(`OCC0,4'hf, 32'h0303_0303);
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m0.wb_wr1(`OCC1,4'hf, 32'h0000_0303);
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m0.wb_wr1(`OCC1,4'hf, 32'h0000_0303);
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m0.wb_wr1(`ICC,4'hf, 32'h0003_0303);
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m0.wb_wr1(`ICC,4'hf, 32'h0003_0303);
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end
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end
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endcase
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endcase
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`ifdef AC97_OUT_FIFO_DEPTH_8
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oc0_th = oc0_th * 2;
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oc1_th = oc1_th * 2;
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oc2_th = oc2_th * 2;
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oc3_th = oc3_th * 2;
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oc4_th = oc4_th * 2;
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oc5_th = oc5_th * 2;
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`endif
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`ifdef AC97_OUT_FIFO_DEPTH_16
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oc0_th = oc0_th * 4;
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oc1_th = oc1_th * 4;
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oc2_th = oc2_th * 4;
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oc3_th = oc3_th * 4;
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oc4_th = oc4_th * 4;
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oc5_th = oc5_th * 4;
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`endif
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`ifdef AC97_IN_FIFO_DEPTH_8
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ic0_th = ic0_th * 2;
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ic1_th = ic1_th * 2;
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ic2_th = ic2_th * 2;
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`endif
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`ifdef AC97_IN_FIFO_DEPTH_16
|
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ic0_th = ic0_th * 4;
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ic1_th = ic1_th * 4;
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ic2_th = ic2_th * 4;
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`endif
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wb_busy = 0;
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wb_busy = 0;
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oc0_dma_en = 0;
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oc0_dma_en = 0;
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oc1_dma_en = 0;
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oc1_dma_en = 0;
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oc2_dma_en = 0;
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oc2_dma_en = 0;
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