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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_defines.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
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// $Id: ac97_defines.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
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//
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//
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// $Date: 2001-08-10 08:09:42 $
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// $Date: 2002-03-05 04:44:05 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/10 08:09:42 rudi
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//
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// - Removed RTY_O output.
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// - Added Clock and Reset Inputs to documentation.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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//
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// Revision 1.1 2001/08/03 06:54:49 rudi
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// Revision 1.1 2001/08/03 06:54:49 rudi
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//
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//
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//
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//
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// - Changed to new directory structure
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// - Changed to new directory structure
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//
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//
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//
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//
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// This is a prescaler that generates a pulse every 250 nS.
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// This is a prescaler that generates a pulse every 250 nS.
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// The value here should one less than the actually calculated
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// The value here should one less than the actually calculated
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// value.
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// value.
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// For a 200 MHz wishbone clock, this value is 49 (50-1).
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// For a 200 MHz wishbone clock, this value is 49 (50-1).
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`define AC97_250_PS 6'd49
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`define AC97_250_PS 6'h31
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// AC97 Cold reset Must be asserted for at least 1uS. The AC97
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// AC97 Cold reset Must be asserted for at least 1uS. The AC97
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// controller will stretch the reset pulse to at least 1uS.
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// controller will stretch the reset pulse to at least 1uS.
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// The reset timer is driven by the AC97_250_PS prescaler.
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// The reset timer is driven by the AC97_250_PS prescaler.
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// This value should probably be never changed. Adjust the
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// This value should probably be never changed. Adjust the
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// AC97_250_PS instead.
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// AC97_250_PS instead.
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`define AC97_RST_DEL 3'd4
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`define AC97_RST_DEL 3'h4
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// This value indicates for how long the resume signaling (asserting sync)
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// This value indicates for how long the resume signaling (asserting sync)
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// should be done. This counter is driven by the AC97_250_PS prescaler.
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// should be done. This counter is driven by the AC97_250_PS prescaler.
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// This value times 250nS is the duration of the resume signaling.
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// This value times 250nS is the duration of the resume signaling.
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// The actual value must be incremented by one, as we do not know
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// The actual value must be incremented by one, as we do not know
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// the current state of the prescaler, and must somehow insure we
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// the current state of the prescaler, and must somehow insure we
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// meet the minimum 1uS length. This value should probably be never
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// meet the minimum 1uS length. This value should probably be never
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// changed. Modify the AC97_250_PS instead.
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// changed. Modify the AC97_250_PS instead.
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`define AC97_RES_SIG 3'd5
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`define AC97_RES_SIG 3'h5
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// If the bit clock is absent for at least two "predicted" bit
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// If the bit clock is absent for at least two "predicted" bit
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// clock periods (163 nS) we should signal "suspended".
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// clock periods (163 nS) we should signal "suspended".
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// This value defines how many WISHBONE cycles must pass without
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// This value defines how many WISHBONE cycles must pass without
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// any change on the bit clock input before we signal "suspended".
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// any change on the bit clock input before we signal "suspended".
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// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
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// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
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`define AC97_SUSP_DET 6'd33
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`define AC97_SUSP_DET 6'h21
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