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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_fifo_ctrl.v] - Diff between revs 4 and 10

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Rev 4 Rev 10
Line 36... Line 36...
////                                                             ////
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/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
//  CVS Log
//
//
//  $Id: ac97_fifo_ctrl.v,v 1.1 2001-08-03 06:54:49 rudi Exp $
//  $Id: ac97_fifo_ctrl.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
//
//  $Date: 2001-08-03 06:54:49 $
//  $Date: 2002-03-05 04:44:05 $
//  $Revision: 1.1 $
//  $Revision: 1.2 $
//  $Author: rudi $
//  $Author: rudi $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.1  2001/08/03 06:54:49  rudi
 
//
 
//
 
//               - Changed to new directory structure
 
//
//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
//               Initial Checkin
//               Initial Checkin
//
//
//
//
//
//
Line 87... Line 92...
always @(posedge clk)
always @(posedge clk)
        if(!valid)      full_empty_r <= #1 full_empty;
        if(!valid)      full_empty_r <= #1 full_empty;
 
 
always @(posedge clk)
always @(posedge clk)
        if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
        if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
                en_out_l <= #1 1;
                en_out_l <= #1 1'b1;
        else
        else
        if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
        if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
                en_out_l <= #1 0;
                en_out_l <= #1 1'b0;
 
 
always @(posedge clk)
always @(posedge clk)
        en_out_l2 <= #1 en_out_l & valid;
        en_out_l2 <= #1 en_out_l & valid;
 
 
assign en_out = en_out_l & !en_out_l2 & valid;
assign en_out = en_out_l & !en_out_l2 & valid;

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