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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_in_fifo.v] - Diff between revs 4 and 10
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_in_fifo.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
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// $Id: ac97_in_fifo.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
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//
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//
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// $Date: 2001-08-03 06:54:50 $
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// $Date: 2002-03-05 04:44:05 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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// - Changed to new directory structure
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//
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// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
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// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
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// Initial Checkin
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// Initial Checkin
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//
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//
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//
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//
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//
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assign m16b = (mode == 2'h0); // 16 Bit Mode
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assign m16b = (mode == 2'h0); // 16 Bit Mode
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always @(posedge clk)
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always @(posedge clk)
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if(!en) wp <= #1 0;
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if(!en) wp <= #1 4'h0;
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else
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else
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if(we) wp <= #1 wp_p1;
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if(we) wp <= #1 wp_p1;
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assign wp_p1 = m16b ? (wp + 1) : (wp + 2);
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assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
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always @(posedge clk)
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always @(posedge clk)
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if(!en) rp <= #1 0;
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if(!en) rp <= #1 3'h0;
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else
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else
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if(re) rp <= #1 rp + 1;
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if(re) rp <= #1 rp + 3'h1;
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always @(posedge clk)
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always @(posedge clk)
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status <= #1 ((rp - wp[2:1]) - 1);
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status <= #1 ((rp - wp[2:1]) - 2'h1);
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always @(posedge clk)
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always @(posedge clk)
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empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
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empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
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always @(posedge clk)
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always @(posedge clk)
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