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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_in_fifo.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
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// $Id: ac97_in_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $
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//
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//
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// $Date: 2002-03-05 04:44:05 $
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// $Date: 2002-03-11 03:21:22 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/03/05 04:44:05 rudi
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//
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Many minor synthesis cleanup items ...
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//
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// Revision 1.1 2001/08/03 06:54:50 rudi
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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//
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//
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// - Changed to new directory structure
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// - Changed to new directory structure
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//
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//
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//
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//
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//
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//
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`include "ac97_defines.v"
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`include "ac97_defines.v"
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`ifdef AC97_IN_FIFO_DEPTH_4
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// 4 entry deep verion of the input FIFO
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module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
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module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
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input clk, rst;
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input clk, rst;
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input en;
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input en;
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input [1:0] mode;
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input [1:0] mode;
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if(!en) rp <= #1 3'h0;
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if(!en) rp <= #1 3'h0;
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else
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else
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if(re) rp <= #1 rp + 3'h1;
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if(re) rp <= #1 rp + 3'h1;
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always @(posedge clk)
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always @(posedge clk)
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status <= #1 ((rp - wp[2:1]) - 2'h1);
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status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
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always @(posedge clk)
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always @(posedge clk)
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empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
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empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
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always @(posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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always @(mode or din_tmp1 or din)
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always @(mode or din_tmp1 or din)
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case(mode) // synopsys parallel_case full_case
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case(mode) // synopsys parallel_case full_case
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0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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`endif
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`ifdef AC97_IN_FIFO_DEPTH_8
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// 8 entry deep verion of the input FIFO
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module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
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input clk, rst;
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input en;
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input [1:0] mode;
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input [19:0] din;
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input we;
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output [31:0] dout;
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input re;
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output [1:0] status;
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output full;
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output empty;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg [31:0] mem[0:7];
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reg [31:0] dout;
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reg [4:0] wp;
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reg [3:0] rp;
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wire [4:0] wp_p1;
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reg [1:0] status;
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reg [15:0] din_tmp1;
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reg [31:0] din_tmp;
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wire m16b;
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reg full, empty;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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assign m16b = (mode == 2'h0); // 16 Bit Mode
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always @(posedge clk)
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if(!en) wp <= #1 5'h0;
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else
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if(we) wp <= #1 wp_p1;
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assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);
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always @(posedge clk)
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if(!en) rp <= #1 4'h0;
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else
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if(re) rp <= #1 rp + 4'h1;
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always @(posedge clk)
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status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);
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always @(posedge clk)
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empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);
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always @(posedge clk)
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full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);
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// Fifo Output
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always @(posedge clk)
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dout <= #1 mem[ rp[2:0] ];
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// Fifo Input Half Word Latch
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always @(posedge clk)
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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always @(mode or din_tmp1 or din)
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case(mode) // synopsys parallel_case full_case
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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endcase
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always @(posedge clk)
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;
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endmodule
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`endif
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`ifdef AC97_IN_FIFO_DEPTH_16
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// 16 entry deep verion of the input FIFO
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module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
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input clk, rst;
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input en;
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input [1:0] mode;
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input [19:0] din;
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input we;
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output [31:0] dout;
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input re;
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output [1:0] status;
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output full;
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output empty;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg [31:0] mem[0:15];
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reg [31:0] dout;
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reg [5:0] wp;
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reg [4:0] rp;
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wire [5:0] wp_p1;
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reg [1:0] status;
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reg [15:0] din_tmp1;
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reg [31:0] din_tmp;
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wire m16b;
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reg full, empty;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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assign m16b = (mode == 2'h0); // 16 Bit Mode
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always @(posedge clk)
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if(!en) wp <= #1 6'h0;
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else
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if(we) wp <= #1 wp_p1;
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assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);
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always @(posedge clk)
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if(!en) rp <= #1 5'h0;
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else
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if(re) rp <= #1 rp + 5'h1;
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always @(posedge clk)
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status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);
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always @(posedge clk)
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empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);
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always @(posedge clk)
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full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);
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// Fifo Output
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always @(posedge clk)
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dout <= #1 mem[ rp[3:0] ];
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// Fifo Input Half Word Latch
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always @(posedge clk)
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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always @(mode or din_tmp1 or din)
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case(mode) // synopsys parallel_case full_case
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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endcase
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always @(posedge clk)
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;
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endmodule
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`endif
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