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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_in_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $
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// $Id: ac97_in_fifo.v,v 1.5 2002-11-14 17:10:12 rudi Exp $
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//
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//
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// $Date: 2002-09-19 06:30:56 $
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// $Date: 2002-11-14 17:10:12 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/19 06:30:56 rudi
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// Fixed a bug reported by Igor. Apparently this bug only shows up when
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// the WB clock is very low (2x bit_clk). Updated Copyright header.
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//
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// Revision 1.3 2002/03/11 03:21:22 rudi
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// Revision 1.3 2002/03/11 03:21:22 rudi
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//
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//
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// - Added defines to select fifo depth between 4, 8 and 16 entries.
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// - Added defines to select fifo depth between 4, 8 and 16 entries.
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//
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//
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// Revision 1.2 2002/03/05 04:44:05 rudi
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// Revision 1.2 2002/03/05 04:44:05 rudi
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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always @(mode or din_tmp1 or din)
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always @(mode or din_tmp1 or din)
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case(mode) // synopsys parallel_case full_case
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case(mode) // synopsys parallel_case full_case
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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always @(mode or din_tmp1 or din)
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always @(mode or din_tmp1 or din)
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case(mode) // synopsys parallel_case full_case
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case(mode) // synopsys parallel_case full_case
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
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always @(mode or din_tmp1 or din)
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always @(mode or din_tmp1 or din)
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case(mode) // synopsys parallel_case full_case
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case(mode) // synopsys parallel_case full_case
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
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2'h1: din_tmp = {13'h0, din[17:0]}; // 18 bit Output
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2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;
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if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;
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