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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_int.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
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// $Id: ac97_int.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
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//
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//
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// $Date: 2001-08-03 06:54:50 $
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// $Date: 2002-03-05 04:44:05 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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// - Changed to new directory structure
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//
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// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
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// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
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// Initial Checkin
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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//
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//
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// Interrupt Logic
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// Interrupt Logic
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//
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//
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) int_set[0] <= #1 0;
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if(!rst) int_set[0] <= #1 1'b0;
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else
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else
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case(cfg[5:4]) // synopsys parallel_case full_case
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case(cfg[5:4]) // synopsys parallel_case full_case
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// 1/4 full/empty
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// 1/4 full/empty
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0: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'd0));
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2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0));
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// 1/2 full/empty
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// 1/2 full/empty
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1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'd0));
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2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0));
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// 3/4 full/empty
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// 3/4 full/empty
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2: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'd3));
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2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3));
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3: int_set[0] <= #1 cfg[0] & full_empty;
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2'h3: int_set[0] <= #1 cfg[0] & full_empty;
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endcase
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endcase
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) int_set[1] <= #1 0;
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if(!rst) int_set[1] <= #1 1'b0;
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else
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else
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if(empty & re) int_set[1] <= #1 1;
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if(empty & re) int_set[1] <= #1 1'b1;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) int_set[2] <= #1 0;
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if(!rst) int_set[2] <= #1 1'b0;
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else
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else
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if(full & we) int_set[2] <= #1 1;
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if(full & we) int_set[2] <= #1 1'b1;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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