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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_rf.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
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// $Id: ac97_rf.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
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//
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//
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// $Date: 2001-08-10 08:09:42 $
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// $Date: 2002-03-05 04:44:05 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/10 08:09:42 rudi
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//
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// - Removed RTY_O output.
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// - Added Clock and Reset Inputs to documentation.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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//
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// Revision 1.1 2001/08/03 06:54:50 rudi
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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//
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//
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// - Changed to new directory structure
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// - Changed to new directory structure
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//
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//
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5: rf_dout = intm;
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5: rf_dout = intm;
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6: rf_dout = ints;
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6: rf_dout = ints;
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endcase
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endcase
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) csr_r <= #1 0;
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if(!rst) csr_r <= #1 1'b0;
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else
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else
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if(rf_we & (adr[2:0]==0)) csr_r <= #1 rf_din;
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if(rf_we & (adr[2:0]==3'h0)) csr_r <= #1 rf_din;
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always @(posedge clk)
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always @(posedge clk)
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if(rf_we & (adr[2:0]==0)) ac97_rst_force <= #1 rf_din[0];
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if(rf_we & (adr[2:0]==3'h0)) ac97_rst_force <= #1 rf_din[0];
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else ac97_rst_force <= #1 0;
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else ac97_rst_force <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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if(rf_we & (adr[2:0]==0)) resume_req <= #1 rf_din[1];
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if(rf_we & (adr[2:0]==3'h0)) resume_req <= #1 rf_din[1];
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else resume_req <= #1 0;
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else resume_req <= #1 1'b0;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) occ0_r <= #1 0;
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if(!rst) occ0_r <= #1 1'b0;
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else
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else
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if(rf_we & (adr[2:0]==1)) occ0_r <= #1 rf_din;
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if(rf_we & (adr[2:0]==3'h1)) occ0_r <= #1 rf_din;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) occ1_r <= #1 0;
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if(!rst) occ1_r <= #1 1'b0;
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else
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else
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if(rf_we & (adr[2:0]==2)) occ1_r <= #1 rf_din[23:0];
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if(rf_we & (adr[2:0]==3'h2)) occ1_r <= #1 rf_din[23:0];
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) icc_r <= #1 0;
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if(!rst) icc_r <= #1 1'b0;
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else
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else
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if(rf_we & (adr[2:0]==3)) icc_r <= #1 rf_din[23:0];
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if(rf_we & (adr[2:0]==3'h3)) icc_r <= #1 rf_din[23:0];
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assign crac_we = rf_we & (adr[2:0]==4);
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assign crac_we = rf_we & (adr[2:0]==3'h4);
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) crac_r <= #1 0;
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if(!rst) crac_r <= #1 1'b0;
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else
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else
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if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]};
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if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]};
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always @(posedge clk)
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always @(posedge clk)
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if(crac_we) crac_dout_r <= #1 rf_din[15:0];
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if(crac_we) crac_dout_r <= #1 rf_din[15:0];
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) intm_r <= #1 0;
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if(!rst) intm_r <= #1 1'b0;
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else
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else
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if(rf_we & (adr[2:0]==5)) intm_r <= #1 rf_din[28:0];
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if(rf_we & (adr[2:0]==3'h5)) intm_r <= #1 rf_din[28:0];
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// Interrupt Source Register
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// Interrupt Source Register
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ints_r <= #1 0;
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if(!rst) ints_r <= #1 1'b0;
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else
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else
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if(rf_re & (adr[2:0]==6)) ints_r <= #1 0;
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if(rf_re & (adr[2:0]==3'h6)) ints_r <= #1 1'b0;
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else
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else
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begin
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begin
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if(crac_rd_done) ints_r[0] <= #1 1;
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if(crac_rd_done) ints_r[0] <= #1 1'b1;
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if(crac_wr_done) ints_r[1] <= #1 1;
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if(crac_wr_done) ints_r[1] <= #1 1'b1;
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if(oc0_int_set[0]) ints_r[2] <= #1 1;
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if(oc0_int_set[0]) ints_r[2] <= #1 1'b1;
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if(oc0_int_set[1]) ints_r[3] <= #1 1;
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if(oc0_int_set[1]) ints_r[3] <= #1 1'b1;
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if(oc0_int_set[2]) ints_r[4] <= #1 1;
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if(oc0_int_set[2]) ints_r[4] <= #1 1'b1;
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if(oc1_int_set[0]) ints_r[5] <= #1 1;
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if(oc1_int_set[0]) ints_r[5] <= #1 1'b1;
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if(oc1_int_set[1]) ints_r[6] <= #1 1;
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if(oc1_int_set[1]) ints_r[6] <= #1 1'b1;
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if(oc1_int_set[2]) ints_r[7] <= #1 1;
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if(oc1_int_set[2]) ints_r[7] <= #1 1'b1;
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`ifdef AC97_CENTER
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`ifdef AC97_CENTER
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if(oc2_int_set[0]) ints_r[8] <= #1 1;
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if(oc2_int_set[0]) ints_r[8] <= #1 1'b1;
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if(oc2_int_set[1]) ints_r[9] <= #1 1;
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if(oc2_int_set[1]) ints_r[9] <= #1 1'b1;
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if(oc2_int_set[2]) ints_r[10] <= #1 1;
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if(oc2_int_set[2]) ints_r[10] <= #1 1'b1;
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`endif
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`endif
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`ifdef AC97_SURROUND
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`ifdef AC97_SURROUND
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if(oc3_int_set[0]) ints_r[11] <= #1 1;
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if(oc3_int_set[0]) ints_r[11] <= #1 1'b1;
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if(oc3_int_set[1]) ints_r[12] <= #1 1;
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if(oc3_int_set[1]) ints_r[12] <= #1 1'b1;
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if(oc3_int_set[2]) ints_r[13] <= #1 1;
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if(oc3_int_set[2]) ints_r[13] <= #1 1'b1;
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if(oc4_int_set[0]) ints_r[14] <= #1 1;
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if(oc4_int_set[0]) ints_r[14] <= #1 1'b1;
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if(oc4_int_set[1]) ints_r[15] <= #1 1;
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if(oc4_int_set[1]) ints_r[15] <= #1 1'b1;
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if(oc4_int_set[2]) ints_r[16] <= #1 1;
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if(oc4_int_set[2]) ints_r[16] <= #1 1'b1;
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`endif
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`endif
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`ifdef AC97_LFE
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`ifdef AC97_LFE
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if(oc5_int_set[0]) ints_r[17] <= #1 1;
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if(oc5_int_set[0]) ints_r[17] <= #1 1'b1;
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if(oc5_int_set[1]) ints_r[18] <= #1 1;
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if(oc5_int_set[1]) ints_r[18] <= #1 1'b1;
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if(oc5_int_set[2]) ints_r[19] <= #1 1;
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if(oc5_int_set[2]) ints_r[19] <= #1 1'b1;
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`endif
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`endif
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`ifdef AC97_SIN
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`ifdef AC97_SIN
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if(ic0_int_set[0]) ints_r[20] <= #1 1;
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if(ic0_int_set[0]) ints_r[20] <= #1 1'b1;
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if(ic0_int_set[1]) ints_r[21] <= #1 1;
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if(ic0_int_set[1]) ints_r[21] <= #1 1'b1;
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if(ic0_int_set[2]) ints_r[22] <= #1 1;
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if(ic0_int_set[2]) ints_r[22] <= #1 1'b1;
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if(ic1_int_set[0]) ints_r[23] <= #1 1;
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if(ic1_int_set[0]) ints_r[23] <= #1 1'b1;
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if(ic1_int_set[1]) ints_r[24] <= #1 1;
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if(ic1_int_set[1]) ints_r[24] <= #1 1'b1;
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if(ic1_int_set[2]) ints_r[25] <= #1 1;
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if(ic1_int_set[2]) ints_r[25] <= #1 1'b1;
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`endif
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`endif
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`ifdef AC97_MICIN
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`ifdef AC97_MICIN
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if(ic2_int_set[0]) ints_r[26] <= #1 1;
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if(ic2_int_set[0]) ints_r[26] <= #1 1'b1;
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if(ic2_int_set[1]) ints_r[27] <= #1 1;
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if(ic2_int_set[1]) ints_r[27] <= #1 1'b1;
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if(ic2_int_set[2]) ints_r[28] <= #1 1;
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if(ic2_int_set[2]) ints_r[28] <= #1 1'b1;
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`endif
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`endif
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end
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end
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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