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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_soc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
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// $Id: ac97_soc.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
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//
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//
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// $Date: 2001-08-03 06:54:50 $
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// $Date: 2002-03-05 04:44:05 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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// - Changed to new directory structure
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//
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// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
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// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
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// Initial Checkin
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// Initial Checkin
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//
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//
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//
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//
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//
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//
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| Line 101... |
Line 106... |
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) cnt <= #1 8'hff;
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if(!rst) cnt <= #1 8'hff;
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else
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else
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if(suspended) cnt <= #1 8'hff;
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if(suspended) cnt <= #1 8'hff;
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else cnt <= #1 cnt + 1;
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else cnt <= #1 cnt + 8'h1;
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always @(posedge clk)
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always @(posedge clk)
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ld <= #1 (cnt == 8'h00);
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ld <= #1 (cnt == 8'h00);
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always @(posedge clk)
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always @(posedge clk)
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sync_beat <= #1 (cnt == 8'h00) | ((cnt > 0) & (cnt < 16));
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sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
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always @(posedge clk)
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always @(posedge clk)
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valid <= #1 (cnt > 57);
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valid <= #1 (cnt > 8'h39);
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always @(posedge clk)
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always @(posedge clk)
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out_le[0] <= #1 (cnt == 8'd17); // Slot 0 Latch Enable
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out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
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always @(posedge clk)
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always @(posedge clk)
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out_le[1] <= #1 (cnt == 8'd37); // Slot 1 Latch Enable
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out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
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always @(posedge clk)
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always @(posedge clk)
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out_le[2] <= #1 (cnt == 8'd57); // Slot 2 Latch Enable
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out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
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always @(posedge clk)
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always @(posedge clk)
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out_le[3] <= #1 (cnt == 8'd77); // Slot 3 Latch Enable
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out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
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always @(posedge clk)
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always @(posedge clk)
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out_le[4] <= #1 (cnt == 8'd97); // Slot 4 Latch Enable
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out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
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always @(posedge clk)
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always @(posedge clk)
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out_le[5] <= #1 (cnt == 8'd137); // Slot 6 Latch Enable
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out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
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always @(posedge clk)
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always @(posedge clk)
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in_valid[0] <= #1 (cnt > 8'd77); // Input Slot 3 Valid
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in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
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always @(posedge clk)
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always @(posedge clk)
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in_valid[1] <= #1 (cnt > 8'd97); // Input Slot 3 Valid
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in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
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always @(posedge clk)
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always @(posedge clk)
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in_valid[2] <= #1 (cnt > 8'd137); // Input Slot 3 Valid
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in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Suspend Detect
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// Suspend Detect
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//
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//
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suspended <= #1 to;
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suspended <= #1 to;
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assign to = (to_cnt == `AC97_SUSP_DET);
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assign to = (to_cnt == `AC97_SUSP_DET);
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always @(posedge wclk or negedge rst)
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always @(posedge wclk or negedge rst)
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if(!rst) to_cnt <= #1 0;
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if(!rst) to_cnt <= #1 6'h0;
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else
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else
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if(bit_clk_e) to_cnt <= #1 0;
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if(bit_clk_e) to_cnt <= #1 6'h0;
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else
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else
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if(!to) to_cnt <= #1 to_cnt + 1;
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if(!to) to_cnt <= #1 to_cnt + 6'h1;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Resume Signaling
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// Resume Signaling
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//
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//
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always @(posedge wclk or negedge rst)
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always @(posedge wclk or negedge rst)
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if(!rst) sync_resume <= #1 0;
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if(!rst) sync_resume <= #1 1'b0;
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else
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else
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if(resume_done) sync_resume <= #1 0;
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if(resume_done) sync_resume <= #1 1'b0;
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else
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else
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if(suspended & resume) sync_resume <= #1 1;
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if(suspended & resume) sync_resume <= #1 1'b1;
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assign resume_done = (res_cnt == `AC97_RES_SIG);
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assign resume_done = (res_cnt == `AC97_RES_SIG);
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always @(posedge wclk)
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always @(posedge wclk)
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if(!sync_resume) res_cnt <= #1 0;
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if(!sync_resume) res_cnt <= #1 4'h0;
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else
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else
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if(ps_ce) res_cnt <= #1 res_cnt + 1;
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if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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