OpenCores

Rev 6	Rev 10
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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: ac97_top.v,v 1.2 2001-08-10 08:09:42 rudi Exp $`	`// $Id: ac97_top.v,v 1.3 2002-03-05 04:44:05 rudi Exp $`
`//`	`//`
`// $Date: 2001-08-10 08:09:42 $`	`// $Date: 2002-03-05 04:44:05 $`
`// $Revision: 1.2 $`	`// $Revision: 1.3 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2001/08/10 08:09:42 rudi`
	`//`
	`// - Removed RTY_O output.`
	`// - Added Clock and Reset Inputs to documentation.`
	`// - Changed IO names to be more clear.`
	`// - Uniquifyed define names to be core specific.`
	`//`
`// Revision 1.1 2001/08/03 06:54:50 rudi`	`// Revision 1.1 2001/08/03 06:54:50 rudi`
`//`	`//`
`//`	`//`
`// - Changed to new directory structure`	`// - Changed to new directory structure`
`//`	`//`
Line 312...	Line 319...
`.status( o6_status ),`	`.status( o6_status ),`
`.full( o6_full ),`	`.full( o6_full ),`
`.empty( o6_empty )`	`.empty( o6_empty )`
`);`	`);`
`else	`else
`assign out_slt6 = 0;`	`assign out_slt6 = 20'h0;`
`assign o6_status = 0;`	`assign o6_status = 2'h0;`
`assign o6_full = 0;`	`assign o6_full = 1'b0;`
`assign o6_empty = 0;`	`assign o6_empty = 1'b0;`
`endif	`endif

`ifdef AC97_SURROUND	`ifdef AC97_SURROUND
`ac97_out_fifo u6(`	`ac97_out_fifo u6(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 347...	Line 354...
`.status( o8_status ),`	`.status( o8_status ),`
`.full( o8_full ),`	`.full( o8_full ),`
`.empty( o8_empty )`	`.empty( o8_empty )`
`);`	`);`
`else	`else
`assign out_slt7 = 0;`	`assign out_slt7 = 20'h0;`
`assign o7_status = 0;`	`assign o7_status = 2'h0;`
`assign o7_full = 0;`	`assign o7_full = 1'b0;`
`assign o7_empty = 0;`	`assign o7_empty = 1'b0;`
`assign out_slt8 = 0;`	`assign out_slt8 = 20'h0;`
`assign o8_status = 0;`	`assign o8_status = 2'h0;`
`assign o8_full = 0;`	`assign o8_full = 1'b0;`
`assign o8_empty = 0;`	`assign o8_empty = 1'b0;`
`endif	`endif

`ifdef AC97_LFE	`ifdef AC97_LFE
`ac97_out_fifo u8(`	`ac97_out_fifo u8(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 372...	Line 379...
`.status( o9_status ),`	`.status( o9_status ),`
`.full( o9_full ),`	`.full( o9_full ),`
`.empty( o9_empty )`	`.empty( o9_empty )`
`);`	`);`
`else	`else
`assign out_slt9 = 0;`	`assign out_slt9 = 20'h0;`
`assign o9_status = 0;`	`assign o9_status = 2'h0;`
`assign o9_full = 0;`	`assign o9_full = 1'b0;`
`assign o9_empty = 0;`	`assign o9_empty = 1'b0;`
`endif	`endif

`ifdef AC97_SIN	`ifdef AC97_SIN
`ac97_in_fifo u9(`	`ac97_in_fifo u9(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 407...	Line 414...
`.status( i4_status ),`	`.status( i4_status ),`
`.full( i4_full ),`	`.full( i4_full ),`
`.empty( i4_empty )`	`.empty( i4_empty )`
`);`	`);`
`else	`else
`assign i3_dout = 0;`	`assign i3_dout = 20'h0;`
`assign i3_status = 0;`	`assign i3_status = 2'h0;`
`assign i3_full = 0;`	`assign i3_full = 1'b0;`
`assign i3_empty = 0;`	`assign i3_empty = 1'b0;`
`assign i4_dout = 0;`	`assign i4_dout = 20'h0;`
`assign i4_status = 0;`	`assign i4_status = 2'h0;`
`assign i4_full = 0;`	`assign i4_full = 1'b0;`
`assign i4_empty = 0;`	`assign i4_empty = 1'b0;`
`endif	`endif

`ifdef AC97_MICIN	`ifdef AC97_MICIN
`ac97_in_fifo u11(`	`ac97_in_fifo u11(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 432...	Line 439...
`.status( i6_status ),`	`.status( i6_status ),`
`.full( i6_full ),`	`.full( i6_full ),`
`.empty( i6_empty )`	`.empty( i6_empty )`
`);`	`);`
`else	`else
`assign i6_dout = 0;`	`assign i6_dout = 20'h0;`
`assign i6_status = 0;`	`assign i6_status = 2'h0;`
`assign i6_full = 0;`	`assign i6_full = 1'b0;`
`assign i6_empty = 0;`	`assign i6_empty = 1'b0;`
`endif	`endif

`ac97_wb_if u12(`	`ac97_wb_if u12(`
`.clk( clk_i ),`	`.clk( clk_i ),`
`.rst( rst_i ),`	`.rst( rst_i ),`
Line 631...	Line 638...
`.empty( o6_empty ),`	`.empty( o6_empty ),`
`.re( o6_re ),`	`.re( o6_re ),`
`.we( o6_we )`	`.we( o6_we )`
`);`	`);`
`else	`else
`assign oc2_int_set = 0;`	`assign oc2_int_set = 1'b0;`
`endif	`endif

`ifdef AC97_SURROUND	`ifdef AC97_SURROUND
`ac97_int u20(`	`ac97_int u20(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 661...	Line 668...
`.empty( o8_empty ),`	`.empty( o8_empty ),`
`.re( o8_re ),`	`.re( o8_re ),`
`.we( o8_we )`	`.we( o8_we )`
`);`	`);`
`else	`else
`assign oc3_int_set = 0;`	`assign oc3_int_set = 1'b0;`
`assign oc4_int_set = 0;`	`assign oc4_int_set = 1'b0;`
`endif	`endif

`ifdef AC97_LFE	`ifdef AC97_LFE
`ac97_int u22(`	`ac97_int u22(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 679...	Line 686...
`.empty( o9_empty ),`	`.empty( o9_empty ),`
`.re( o9_re ),`	`.re( o9_re ),`
`.we( o9_we )`	`.we( o9_we )`
`);`	`);`
`else	`else
`assign oc5_int_set = 0;`	`assign oc5_int_set = 1'b0;`
`endif	`endif

`ifdef AC97_SIN	`ifdef AC97_SIN
`ac97_int u23(`	`ac97_int u23(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 709...	Line 716...
`.empty( i4_empty ),`	`.empty( i4_empty ),`
`.re( i4_re ),`	`.re( i4_re ),`
`.we( i4_we )`	`.we( i4_we )`
`);`	`);`
`else	`else
`assign ic0_int_set = 0;`	`assign ic0_int_set = 1'b0;`
`assign ic1_int_set = 0;`	`assign ic1_int_set = 1'b0;`
`endif	`endif

`ifdef AC97_MICIN	`ifdef AC97_MICIN
`ac97_int u25(`	`ac97_int u25(`
`.clk( clk_i ),`	`.clk( clk_i ),`
Line 727...	Line 734...
`.empty( i6_empty ),`	`.empty( i6_empty ),`
`.re( i6_re ),`	`.re( i6_re ),`
`.we( i6_we )`	`.we( i6_we )`
`);`	`);`
`else	`else
`assign ic2_int_set = 0;`	`assign ic2_int_set = 1'b0;`
`endif	`endif

`ac97_rst u26(`	`ac97_rst u26(`
`.clk( clk_i ),`	`.clk( clk_i ),`
`.rst( rst_i ),`	`.rst( rst_i ),`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: ac97_top.v,v 1.2 2001-08-10 08:09:42 rudi Exp $

//  $Id: ac97_top.v,v 1.3 2002-03-05 04:44:05 rudi Exp $

//

//

//  $Date: 2001-08-10 08:09:42 $

//  $Date: 2002-03-05 04:44:05 $

//  $Revision: 1.2 $

//  $Revision: 1.3 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.2  2001/08/10 08:09:42  rudi

//

//               - Removed RTY_O output.

//               - Added Clock and Reset Inputs to documentation.

//               - Changed IO names to be more clear.

//               - Uniquifyed define names to be core specific.

//

//               Revision 1.1  2001/08/03 06:54:50  rudi

//               Revision 1.1  2001/08/03 06:54:50  rudi

//

//

//

//

//               - Changed to new directory structure

//               - Changed to new directory structure

//

//

Line 312...

Line 319...

                .status(        o6_status       ),

                .status(        o6_status       ),

                .full(          o6_full         ),

                .full(          o6_full         ),

                .empty(         o6_empty        )

                .empty(         o6_empty        )

);

);

`else

`else

assign out_slt6 = 0;

assign out_slt6 = 20'h0;

assign o6_status = 0;

assign o6_status = 2'h0;

assign o6_full = 0;

assign o6_full = 1'b0;

assign o6_empty = 0;

assign o6_empty = 1'b0;

`endif

`endif

`ifdef AC97_SURROUND

`ifdef AC97_SURROUND

ac97_out_fifo   u6(

ac97_out_fifo   u6(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 347...

Line 354...

                .status(        o8_status       ),

                .status(        o8_status       ),

                .full(          o8_full         ),

                .full(          o8_full         ),

                .empty(         o8_empty        )

                .empty(         o8_empty        )

);

);

`else

`else

assign out_slt7 = 0;

assign out_slt7 = 20'h0;

assign o7_status = 0;

assign o7_status = 2'h0;

assign o7_full = 0;

assign o7_full = 1'b0;

assign o7_empty = 0;

assign o7_empty = 1'b0;

assign out_slt8 = 0;

assign out_slt8 = 20'h0;

assign o8_status = 0;

assign o8_status = 2'h0;

assign o8_full = 0;

assign o8_full = 1'b0;

assign o8_empty = 0;

assign o8_empty = 1'b0;

`endif

`endif

`ifdef AC97_LFE

`ifdef AC97_LFE

ac97_out_fifo   u8(

ac97_out_fifo   u8(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 372...

Line 379...

                .status(        o9_status       ),

                .status(        o9_status       ),

                .full(          o9_full         ),

                .full(          o9_full         ),

                .empty(         o9_empty        )

                .empty(         o9_empty        )

);

);

`else

`else

assign out_slt9 = 0;

assign out_slt9 = 20'h0;

assign o9_status = 0;

assign o9_status = 2'h0;

assign o9_full = 0;

assign o9_full = 1'b0;

assign o9_empty = 0;

assign o9_empty = 1'b0;

`endif

`endif

`ifdef AC97_SIN

`ifdef AC97_SIN

ac97_in_fifo    u9(

ac97_in_fifo    u9(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 407...

Line 414...

                .status(        i4_status       ),

                .status(        i4_status       ),

                .full(          i4_full         ),

                .full(          i4_full         ),

                .empty(         i4_empty        )

                .empty(         i4_empty        )

);

);

`else

`else

assign i3_dout = 0;

assign i3_dout = 20'h0;

assign i3_status = 0;

assign i3_status = 2'h0;

assign i3_full = 0;

assign i3_full = 1'b0;

assign i3_empty = 0;

assign i3_empty = 1'b0;

assign i4_dout = 0;

assign i4_dout = 20'h0;

assign i4_status = 0;

assign i4_status = 2'h0;

assign i4_full = 0;

assign i4_full = 1'b0;

assign i4_empty = 0;

assign i4_empty = 1'b0;

`endif

`endif

`ifdef AC97_MICIN

`ifdef AC97_MICIN

ac97_in_fifo    u11(

ac97_in_fifo    u11(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 432...

Line 439...

                .status(        i6_status       ),

                .status(        i6_status       ),

                .full(          i6_full         ),

                .full(          i6_full         ),

                .empty(         i6_empty        )

                .empty(         i6_empty        )

);

);

`else

`else

assign i6_dout = 0;

assign i6_dout = 20'h0;

assign i6_status = 0;

assign i6_status = 2'h0;

assign i6_full = 0;

assign i6_full = 1'b0;

assign i6_empty = 0;

assign i6_empty = 1'b0;

`endif

`endif

ac97_wb_if      u12(

ac97_wb_if      u12(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

                .rst(           rst_i           ),

                .rst(           rst_i           ),

Line 631...

Line 638...

                .empty(         o6_empty        ),

                .empty(         o6_empty        ),

                .re(            o6_re           ),

                .re(            o6_re           ),

                .we(            o6_we           )

                .we(            o6_we           )

);

);

`else

`else

assign oc2_int_set = 0;

assign oc2_int_set = 1'b0;

`endif

`endif

`ifdef AC97_SURROUND

`ifdef AC97_SURROUND

ac97_int        u20(

ac97_int        u20(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 661...

Line 668...

                .empty(         o8_empty        ),

                .empty(         o8_empty        ),

                .re(            o8_re           ),

                .re(            o8_re           ),

                .we(            o8_we           )

                .we(            o8_we           )

);

);

`else

`else

assign oc3_int_set = 0;

assign oc3_int_set = 1'b0;

assign oc4_int_set = 0;

assign oc4_int_set = 1'b0;

`endif

`endif

`ifdef AC97_LFE

`ifdef AC97_LFE

ac97_int        u22(

ac97_int        u22(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 679...

Line 686...

                .empty(         o9_empty        ),

                .empty(         o9_empty        ),

                .re(            o9_re           ),

                .re(            o9_re           ),

                .we(            o9_we           )

                .we(            o9_we           )

);

);

`else

`else

assign oc5_int_set = 0;

assign oc5_int_set = 1'b0;

`endif

`endif

`ifdef AC97_SIN

`ifdef AC97_SIN

ac97_int        u23(

ac97_int        u23(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 709...

Line 716...

                .empty(         i4_empty        ),

                .empty(         i4_empty        ),

                .re(            i4_re           ),

                .re(            i4_re           ),

                .we(            i4_we           )

                .we(            i4_we           )

);

);

`else

`else

assign ic0_int_set = 0;

assign ic0_int_set = 1'b0;

assign ic1_int_set = 0;

assign ic1_int_set = 1'b0;

`endif

`endif

`ifdef AC97_MICIN

`ifdef AC97_MICIN

ac97_int        u25(

ac97_int        u25(

                .clk(           clk_i           ),

                .clk(           clk_i           ),

Line 727...

Line 734...

                .empty(         i6_empty        ),

                .empty(         i6_empty        ),

                .re(            i6_re           ),

                .re(            i6_re           ),

                .we(            i6_we           )

                .we(            i6_we           )

);

);

`else

`else

assign ic2_int_set = 0;

assign ic2_int_set = 1'b0;

`endif

`endif

ac97_rst        u26(

ac97_rst        u26(

                .clk(           clk_i                           ),

                .clk(           clk_i                           ),

                .rst(           rst_i                           ),

                .rst(           rst_i                           ),

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