OpenCores

Rev 4	Rev 6
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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: ac97_top.v,v 1.1 2001-08-03 06:54:50 rudi Exp $`	`// $Id: ac97_top.v,v 1.2 2001-08-10 08:09:42 rudi Exp $`
`//`	`//`
`// $Date: 2001-08-03 06:54:50 $`	`// $Date: 2001-08-10 08:09:42 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/08/03 06:54:50 rudi`
	`//`
	`//`
	`// - Changed to new directory structure`
	`//`
`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`	`// Revision 1.1.1.1 2001/05/19 02:29:14 rudi`
`// Initial Checkin`	`// Initial Checkin`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

`include "ac97_defines.v"	`include "ac97_defines.v"

`module ac97_top(clk, rst,`	`module ac97_top(clk_i, rst_i,`

`wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,`	`wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
`wb_stb_i, wb_ack_o, wb_err_o,`	`wb_stb_i, wb_ack_o, wb_err_o,`

`int, dma_req, dma_ack,`	`int_o, dma_req_o, dma_ack_i,`
`suspended,`	`suspended_o,`

`bit_clk, sync, sdata_out, sdata_in, ac97_reset_`	`bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,`
	`ac97_reset_pad_o_`
`);`	`);`

`input clk, rst;`	`input clk_i, rst_i;`

`// --------------------------------------`	`// --------------------------------------`
`// WISHBONE SLAVE INTERFACE`	`// WISHBONE SLAVE INTERFACE`
`input [31:0] wb_data_i;`	`input [31:0] wb_data_i;`
`output [31:0] wb_data_o;`	`output [31:0] wb_data_o;`
Line 81...	Line 87...
`output wb_ack_o;`	`output wb_ack_o;`
`output wb_err_o;`	`output wb_err_o;`

`// --------------------------------------`	`// --------------------------------------`
`// Misc Signals`	`// Misc Signals`
`output int;`	`output int_o;`
`output [8:0] dma_req;`	`output [8:0] dma_req_o;`
`input [8:0] dma_ack;`	`input [8:0] dma_ack_i;`

`// --------------------------------------`	`// --------------------------------------`
`// Suspend Resume Interface`	`// Suspend Resume Interface`
`output suspended;`	`output suspended_o;`

`// --------------------------------------`	`// --------------------------------------`
`// AC97 Codec Interface`	`// AC97 Codec Interface`
`input bit_clk;`	`input bit_clk_pad_i;`
`output sync;`	`output sync_pad_o;`
`output sdata_out;`	`output sdata_pad_o;`
`input sdata_in;`	`input sdata_pad_i;`
`output ac97_reset_;`	`output ac97_reset_pad_o_;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Local Wires`	`// Local Wires`
`//`	`//`
Line 122...	Line 128...
`wire [19:0] in_slt3;`	`wire [19:0] in_slt3;`
`wire [19:0] in_slt4;`	`wire [19:0] in_slt4;`
`wire [19:0] in_slt6;`	`wire [19:0] in_slt6;`

`// Serial IO Controller Interface`	`// Serial IO Controller Interface`
`wire sync;`
`wire ld;`	`wire ld;`
`wire valid;`	`wire valid;`
`wire [5:0] out_le;`	`wire [5:0] out_le;`
`wire [2:0] in_valid;`	`wire [2:0] in_valid;`
`wire ps_ce;`	`wire ps_ce;`
Line 157...	Line 162...
`wire [3:0] adr;`	`wire [3:0] adr;`
`wire [31:0] rf_dout;`	`wire [31:0] rf_dout;`
`wire [31:0] rf_din;`	`wire [31:0] rf_din;`
`wire rf_we;`	`wire rf_we;`
`wire rf_re;`	`wire rf_re;`
`wire int;`
`wire ac97_rst_force;`	`wire ac97_rst_force;`
`wire resume_req;`	`wire resume_req;`
`wire crac_we;`	`wire crac_we;`
`wire [15:0] crac_din;`	`wire [15:0] crac_din;`
`wire [31:0] crac_out;`	`wire [31:0] crac_out;`
Line 193...	Line 197...
`//`	`//`
`// Misc Logic`	`// Misc Logic`
`//`	`//`

`// Sync Valid to WISHBONE Clock`	`// Sync Valid to WISHBONE Clock`
`always @(posedge clk)`	`always @(posedge clk_i)`
`valid_s1 <= #1 valid;`	`valid_s1 <= #1 valid;`

`always @(posedge clk)`	`always @(posedge clk_i)`
`valid_s <= #1 valid_s1;`	`valid_s <= #1 valid_s1;`

`always @(posedge clk)`	`always @(posedge clk_i)`
`in_valid_s1 <= #1 in_valid;`	`in_valid_s1 <= #1 in_valid;`

`always @(posedge clk)`	`always @(posedge clk_i)`
`in_valid_s <= #1 in_valid_s1;`	`in_valid_s <= #1 in_valid_s1;`

`// "valid_s" Indicates when any of the outputs to the output S/R may`	`// "valid_s" Indicates when any of the outputs to the output S/R may`
`// change or when outputs from input S/R may be sampled`	`// change or when outputs from input S/R may be sampled`
`assign o3_mode = oc0_cfg[3:2];`	`assign o3_mode = oc0_cfg[3:2];`
Line 223...	Line 227...
`//`	`//`
`// Modules`	`// Modules`
`//`	`//`

`ac97_sout u0(`	`ac97_sout u0(`
`.clk( bit_clk ),`	`.clk( bit_clk_pad_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.so_ld( ld ),`	`.so_ld( ld ),`
`.slt0( out_slt0 ),`	`.slt0( out_slt0 ),`
`.slt1( out_slt1 ),`	`.slt1( out_slt1 ),`
`.slt2( out_slt2 ),`	`.slt2( out_slt2 ),`
`.slt3( out_slt3 ),`	`.slt3( out_slt3 ),`
`.slt4( out_slt4 ),`	`.slt4( out_slt4 ),`
`.slt6( out_slt6 ),`	`.slt6( out_slt6 ),`
`.slt7( out_slt7 ),`	`.slt7( out_slt7 ),`
`.slt8( out_slt8 ),`	`.slt8( out_slt8 ),`
`.slt9( out_slt9 ),`	`.slt9( out_slt9 ),`
`.sdata_out( sdata_out )`	`.sdata_out( sdata_pad_o )`
`);`	`);`

`ac97_sin u1(`	`ac97_sin u1(`
`.clk( bit_clk ),`	`.clk( bit_clk_pad_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.out_le( out_le ),`	`.out_le( out_le ),`
`.slt0( in_slt0 ),`	`.slt0( in_slt0 ),`
`.slt1( in_slt1 ),`	`.slt1( in_slt1 ),`
`.slt2( in_slt2 ),`	`.slt2( in_slt2 ),`
`.slt3( in_slt3 ),`	`.slt3( in_slt3 ),`
`.slt4( in_slt4 ),`	`.slt4( in_slt4 ),`
`.slt6( in_slt6 ),`	`.slt6( in_slt6 ),`
`.sdata_in( sdata_in )`	`.sdata_in( sdata_pad_i )`
`);`	`);`

`ac97_soc u2(`	`ac97_soc u2(`
`.clk( bit_clk ),`	`.clk( bit_clk_pad_i ),`
`.wclk( clk ),`	`.wclk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.ps_ce( ps_ce ),`	`.ps_ce( ps_ce ),`
`.resume( resume_req ),`	`.resume( resume_req ),`
`.suspended( suspended ),`	`.suspended( suspended_o ),`
`.sync( sync ),`	`.sync( sync_pad_o ),`
`.out_le( out_le ),`	`.out_le( out_le ),`
`.in_valid( in_valid ),`	`.in_valid( in_valid ),`
`.ld( ld ),`	`.ld( ld ),`
`.valid( valid )`	`.valid( valid )`
`);`	`);`

`ac97_out_fifo u3(`	`ac97_out_fifo u3(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( oc0_cfg[0] ),`	`.en( oc0_cfg[0] ),`
`.mode( o3_mode ),`	`.mode( o3_mode ),`
`.din( wb_din ),`	`.din( wb_din ),`
`.we( o3_we ),`	`.we( o3_we ),`
`.dout( out_slt3 ),`	`.dout( out_slt3 ),`
Line 280...	Line 284...
`.full( o3_full ),`	`.full( o3_full ),`
`.empty( o3_empty )`	`.empty( o3_empty )`
`);`	`);`

`ac97_out_fifo u4(`	`ac97_out_fifo u4(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( oc1_cfg[0] ),`	`.en( oc1_cfg[0] ),`
`.mode( o4_mode ),`	`.mode( o4_mode ),`
`.din( wb_din ),`	`.din( wb_din ),`
`.we( o4_we ),`	`.we( o4_we ),`
`.dout( out_slt4 ),`	`.dout( out_slt4 ),`
Line 293...	Line 297...
`.status( o4_status ),`	`.status( o4_status ),`
`.full( o4_full ),`	`.full( o4_full ),`
`.empty( o4_empty )`	`.empty( o4_empty )`
`);`	`);`

`ifdef CENTER	`ifdef AC97_CENTER
`ac97_out_fifo u5(`	`ac97_out_fifo u5(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( oc2_cfg[0] ),`	`.en( oc2_cfg[0] ),`
`.mode( o6_mode ),`	`.mode( o6_mode ),`
`.din( wb_din ),`	`.din( wb_din ),`
`.we( o6_we ),`	`.we( o6_we ),`
`.dout( out_slt6 ),`	`.dout( out_slt6 ),`
Line 314...	Line 318...
`assign o6_status = 0;`	`assign o6_status = 0;`
`assign o6_full = 0;`	`assign o6_full = 0;`
`assign o6_empty = 0;`	`assign o6_empty = 0;`
`endif	`endif

`ifdef SURROUND	`ifdef AC97_SURROUND
`ac97_out_fifo u6(`	`ac97_out_fifo u6(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( oc3_cfg[0] ),`	`.en( oc3_cfg[0] ),`
`.mode( o7_mode ),`	`.mode( o7_mode ),`
`.din( wb_din ),`	`.din( wb_din ),`
`.we( o7_we ),`	`.we( o7_we ),`
`.dout( out_slt7 ),`	`.dout( out_slt7 ),`
Line 330...	Line 334...
`.full( o7_full ),`	`.full( o7_full ),`
`.empty( o7_empty )`	`.empty( o7_empty )`
`);`	`);`

`ac97_out_fifo u7(`	`ac97_out_fifo u7(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( oc4_cfg[0] ),`	`.en( oc4_cfg[0] ),`
`.mode( o8_mode ),`	`.mode( o8_mode ),`
`.din( wb_din ),`	`.din( wb_din ),`
`.we( o8_we ),`	`.we( o8_we ),`
`.dout( out_slt8 ),`	`.dout( out_slt8 ),`
Line 353...	Line 357...
`assign o8_status = 0;`	`assign o8_status = 0;`
`assign o8_full = 0;`	`assign o8_full = 0;`
`assign o8_empty = 0;`	`assign o8_empty = 0;`
`endif	`endif

`ifdef LFE	`ifdef AC97_LFE
`ac97_out_fifo u8(`	`ac97_out_fifo u8(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( oc5_cfg[0] ),`	`.en( oc5_cfg[0] ),`
`.mode( o9_mode ),`	`.mode( o9_mode ),`
`.din( wb_din ),`	`.din( wb_din ),`
`.we( o9_we ),`	`.we( o9_we ),`
`.dout( out_slt9 ),`	`.dout( out_slt9 ),`
Line 374...	Line 378...
`assign o9_status = 0;`	`assign o9_status = 0;`
`assign o9_full = 0;`	`assign o9_full = 0;`
`assign o9_empty = 0;`	`assign o9_empty = 0;`
`endif	`endif

`ifdef SIN	`ifdef AC97_SIN
`ac97_in_fifo u9(`	`ac97_in_fifo u9(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( ic0_cfg[0] ),`	`.en( ic0_cfg[0] ),`
`.mode( i3_mode ),`	`.mode( i3_mode ),`
`.din( in_slt3 ),`	`.din( in_slt3 ),`
`.we( i3_we ),`	`.we( i3_we ),`
`.dout( i3_dout ),`	`.dout( i3_dout ),`
Line 390...	Line 394...
`.full( i3_full ),`	`.full( i3_full ),`
`.empty( i3_empty )`	`.empty( i3_empty )`
`);`	`);`

`ac97_in_fifo u10(`	`ac97_in_fifo u10(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( ic1_cfg[0] ),`	`.en( ic1_cfg[0] ),`
`.mode( i4_mode ),`	`.mode( i4_mode ),`
`.din( in_slt4 ),`	`.din( in_slt4 ),`
`.we( i4_we ),`	`.we( i4_we ),`
`.dout( i4_dout ),`	`.dout( i4_dout ),`
Line 413...	Line 417...
`assign i4_status = 0;`	`assign i4_status = 0;`
`assign i4_full = 0;`	`assign i4_full = 0;`
`assign i4_empty = 0;`	`assign i4_empty = 0;`
`endif	`endif

`ifdef MICIN	`ifdef AC97_MICIN
`ac97_in_fifo u11(`	`ac97_in_fifo u11(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.en( ic2_cfg[0] ),`	`.en( ic2_cfg[0] ),`
`.mode( i6_mode ),`	`.mode( i6_mode ),`
`.din( in_slt6 ),`	`.din( in_slt6 ),`
`.we( i6_we ),`	`.we( i6_we ),`
`.dout( i6_dout ),`	`.dout( i6_dout ),`
Line 435...	Line 439...
`assign i6_full = 0;`	`assign i6_full = 0;`
`assign i6_empty = 0;`	`assign i6_empty = 0;`
`endif	`endif

`ac97_wb_if u12(`	`ac97_wb_if u12(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.wb_data_i( wb_data_i ),`	`.wb_data_i( wb_data_i ),`
`.wb_data_o( wb_data_o ),`	`.wb_data_o( wb_data_o ),`
`.wb_addr_i( wb_addr_i ),`	`.wb_addr_i( wb_addr_i ),`
`.wb_sel_i( wb_sel_i ),`	`.wb_sel_i( wb_sel_i ),`
`.wb_we_i( wb_we_i ),`	`.wb_we_i( wb_we_i ),`
Line 465...	Line 469...
`.i3_re( i3_re ),`	`.i3_re( i3_re ),`
`.i4_re( i4_re ),`	`.i4_re( i4_re ),`
`.i6_re( i6_re )`	`.i6_re( i6_re )`
`);`	`);`

`ac97_rf u13( .clk( clk ),`	`ac97_rf u13( .clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.adr( adr ),`	`.adr( adr ),`
`.rf_dout( rf_dout ),`	`.rf_dout( rf_dout ),`
`.rf_din( wb_din ),`	`.rf_din( wb_din ),`
`.rf_we( rf_we ),`	`.rf_we( rf_we ),`
`.rf_re( rf_re ),`	`.rf_re( rf_re ),`
`.int( int ),`	`.int( int_o ),`
`.ac97_rst_force(ac97_rst_force ),`	`.ac97_rst_force(ac97_rst_force ),`
`.resume_req( resume_req ),`	`.resume_req( resume_req ),`
`.suspended( suspended ),`	`.suspended( suspended_o ),`
`.crac_we( crac_we ),`	`.crac_we( crac_we ),`
`.crac_din( crac_din ),`	`.crac_din( crac_din ),`
`.crac_out( crac_out ),`	`.crac_out( crac_out ),`
`.crac_wr_done( crac_wr_done ),`	`.crac_wr_done( crac_wr_done ),`
`.crac_rd_done( crac_rd_done ),`	`.crac_rd_done( crac_rd_done ),`
Line 501...	Line 505...
`.ic0_int_set( ic0_int_set ),`	`.ic0_int_set( ic0_int_set ),`
`.ic1_int_set( ic1_int_set ),`	`.ic1_int_set( ic1_int_set ),`
`.ic2_int_set( ic2_int_set )`	`.ic2_int_set( ic2_int_set )`
`);`	`);`

`ac97_prc u14( .clk( clk ),`	`ac97_prc u14( .clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.valid( valid_s ),`	`.valid( valid_s ),`
`.in_valid( in_valid_s ),`	`.in_valid( in_valid_s ),`
`.out_slt0( out_slt0 ),`	`.out_slt0( out_slt0 ),`
`.in_slt0( in_slt0 ),`	`.in_slt0( in_slt0 ),`
`.in_slt1( in_slt1 ),`	`.in_slt1( in_slt1 ),`
Line 539...	Line 543...
`.i3_we( i3_we ),`	`.i3_we( i3_we ),`
`.i4_we( i4_we ),`	`.i4_we( i4_we ),`
`.i6_we( i6_we )`	`.i6_we( i6_we )`
`);`	`);`

`ac97_cra u15( .clk( clk ),`	`ac97_cra u15( .clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.crac_we( crac_we ),`	`.crac_we( crac_we ),`
`.crac_din( crac_din ),`	`.crac_din( crac_din ),`
`.crac_out( crac_out ),`	`.crac_out( crac_out ),`
`.crac_wr_done( crac_wr_done ),`	`.crac_wr_done( crac_wr_done ),`
`.crac_rd_done( crac_rd_done ),`	`.crac_rd_done( crac_rd_done ),`
Line 554...	Line 558...
`.in_slt2( in_slt2 ),`	`.in_slt2( in_slt2 ),`
`.crac_valid( crac_valid ),`	`.crac_valid( crac_valid ),`
`.crac_wr( crac_wr )`	`.crac_wr( crac_wr )`
`);`	`);`

`ac97_dma_if u16(.clk( clk ),`	`ac97_dma_if u16(.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.o3_status( o3_status ),`	`.o3_status( o3_status ),`
`.o4_status( o4_status ),`	`.o4_status( o4_status ),`
`.o6_status( o6_status ),`	`.o6_status( o6_status ),`
`.o7_status( o7_status ),`	`.o7_status( o7_status ),`
`.o8_status( o8_status ),`	`.o8_status( o8_status ),`
Line 583...	Line 587...
`.oc4_cfg( oc4_cfg ),`	`.oc4_cfg( oc4_cfg ),`
`.oc5_cfg( oc5_cfg ),`	`.oc5_cfg( oc5_cfg ),`
`.ic0_cfg( ic0_cfg ),`	`.ic0_cfg( ic0_cfg ),`
`.ic1_cfg( ic1_cfg ),`	`.ic1_cfg( ic1_cfg ),`
`.ic2_cfg( ic2_cfg ),`	`.ic2_cfg( ic2_cfg ),`
`.dma_req( dma_req ),`	`.dma_req( dma_req_o ),`
`.dma_ack( dma_ack )`	`.dma_ack( dma_ack_i )`
`);`	`);`

`ac97_int u17(`	`ac97_int u17(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( oc0_int_set ),`	`.int_set( oc0_int_set ),`
`.cfg( oc0_cfg ),`	`.cfg( oc0_cfg ),`
`.status( o3_status ),`	`.status( o3_status ),`
`.full_empty( o3_empty ),`	`.full_empty( o3_empty ),`
`.full( o3_full ),`	`.full( o3_full ),`
Line 601...	Line 605...
`.re( o3_re ),`	`.re( o3_re ),`
`.we( o3_we )`	`.we( o3_we )`
`);`	`);`

`ac97_int u18(`	`ac97_int u18(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( oc1_int_set ),`	`.int_set( oc1_int_set ),`
`.cfg( oc1_cfg ),`	`.cfg( oc1_cfg ),`
`.status( o4_status ),`	`.status( o4_status ),`
`.full_empty( o4_empty ),`	`.full_empty( o4_empty ),`
`.full( o4_full ),`	`.full( o4_full ),`
`.empty( o4_empty ),`	`.empty( o4_empty ),`
`.re( o4_re ),`	`.re( o4_re ),`
`.we( o4_we )`	`.we( o4_we )`
`);`	`);`

`ifdef CENTER	`ifdef AC97_CENTER
`ac97_int u19(`	`ac97_int u19(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( oc2_int_set ),`	`.int_set( oc2_int_set ),`
`.cfg( oc2_cfg ),`	`.cfg( oc2_cfg ),`
`.status( o6_status ),`	`.status( o6_status ),`
`.full_empty( o6_empty ),`	`.full_empty( o6_empty ),`
`.full( o6_full ),`	`.full( o6_full ),`
Line 630...	Line 634...
`);`	`);`
`else	`else
`assign oc2_int_set = 0;`	`assign oc2_int_set = 0;`
`endif	`endif

`ifdef SURROUND	`ifdef AC97_SURROUND
`ac97_int u20(`	`ac97_int u20(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( oc3_int_set ),`	`.int_set( oc3_int_set ),`
`.cfg( oc3_cfg ),`	`.cfg( oc3_cfg ),`
`.status( o7_status ),`	`.status( o7_status ),`
`.full_empty( o7_empty ),`	`.full_empty( o7_empty ),`
`.full( o7_full ),`	`.full( o7_full ),`
Line 645...	Line 649...
`.re( o7_re ),`	`.re( o7_re ),`
`.we( o7_we )`	`.we( o7_we )`
`);`	`);`

`ac97_int u21(`	`ac97_int u21(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( oc4_int_set ),`	`.int_set( oc4_int_set ),`
`.cfg( oc4_cfg ),`	`.cfg( oc4_cfg ),`
`.status( o8_status ),`	`.status( o8_status ),`
`.full_empty( o8_empty ),`	`.full_empty( o8_empty ),`
`.full( o8_full ),`	`.full( o8_full ),`
Line 661...	Line 665...
`else	`else
`assign oc3_int_set = 0;`	`assign oc3_int_set = 0;`
`assign oc4_int_set = 0;`	`assign oc4_int_set = 0;`
`endif	`endif

`ifdef LFE	`ifdef AC97_LFE
`ac97_int u22(`	`ac97_int u22(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( oc5_int_set ),`	`.int_set( oc5_int_set ),`
`.cfg( oc5_cfg ),`	`.cfg( oc5_cfg ),`
`.status( o9_status ),`	`.status( o9_status ),`
`.full_empty( o9_empty ),`	`.full_empty( o9_empty ),`
`.full( o9_full ),`	`.full( o9_full ),`
Line 678...	Line 682...
`);`	`);`
`else	`else
`assign oc5_int_set = 0;`	`assign oc5_int_set = 0;`
`endif	`endif

`ifdef SIN	`ifdef AC97_SIN
`ac97_int u23(`	`ac97_int u23(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( ic0_int_set ),`	`.int_set( ic0_int_set ),`
`.cfg( ic0_cfg ),`	`.cfg( ic0_cfg ),`
`.status( i3_status ),`	`.status( i3_status ),`
`.full_empty( i3_full ),`	`.full_empty( i3_full ),`
`.full( i3_full ),`	`.full( i3_full ),`
Line 693...	Line 697...
`.re( i3_re ),`	`.re( i3_re ),`
`.we( i3_we )`	`.we( i3_we )`
`);`	`);`

`ac97_int u24(`	`ac97_int u24(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( ic1_int_set ),`	`.int_set( ic1_int_set ),`
`.cfg( ic1_cfg ),`	`.cfg( ic1_cfg ),`
`.status( i4_status ),`	`.status( i4_status ),`
`.full_empty( i4_full ),`	`.full_empty( i4_full ),`
`.full( i4_full ),`	`.full( i4_full ),`
Line 709...	Line 713...
`else	`else
`assign ic0_int_set = 0;`	`assign ic0_int_set = 0;`
`assign ic1_int_set = 0;`	`assign ic1_int_set = 0;`
`endif	`endif

`ifdef MICIN	`ifdef AC97_MICIN
`ac97_int u25(`	`ac97_int u25(`
`.clk( clk ),`	`.clk( clk_i ),`
`.rst( rst ),`	`.rst( rst_i ),`
`.int_set( ic2_int_set ),`	`.int_set( ic2_int_set ),`
`.cfg( ic2_cfg ),`	`.cfg( ic2_cfg ),`
`.status( i6_status ),`	`.status( i6_status ),`
`.full_empty( i6_full ),`	`.full_empty( i6_full ),`
`.full( i6_full ),`	`.full( i6_full ),`
Line 727...	Line 731...
`else	`else
`assign ic2_int_set = 0;`	`assign ic2_int_set = 0;`
`endif	`endif

`ac97_rst u26(`	`ac97_rst u26(`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: ac97_top.v,v 1.1 2001-08-03 06:54:50 rudi Exp $

//  $Id: ac97_top.v,v 1.2 2001-08-10 08:09:42 rudi Exp $

//

//

//  $Date: 2001-08-03 06:54:50 $

//  $Date: 2001-08-10 08:09:42 $

//  $Revision: 1.1 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.1  2001/08/03 06:54:50  rudi

//

//

//               - Changed to new directory structure

//

//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi

//               Revision 1.1.1.1  2001/05/19 02:29:14  rudi

//               Initial Checkin

//               Initial Checkin

//

//

//

//

//

//

//

//

`include "ac97_defines.v"

`include "ac97_defines.v"

module ac97_top(clk, rst,

module ac97_top(clk_i, rst_i,

        wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,

        wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,

        wb_stb_i, wb_ack_o, wb_err_o,

        wb_stb_i, wb_ack_o, wb_err_o,

        int, dma_req, dma_ack,

        int_o, dma_req_o, dma_ack_i,

        suspended,

        suspended_o,

        bit_clk, sync, sdata_out, sdata_in, ac97_reset_

        bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,

        ac97_reset_pad_o_

);

);

input           clk, rst;

input           clk_i, rst_i;

// --------------------------------------

// --------------------------------------

// WISHBONE SLAVE INTERFACE

// WISHBONE SLAVE INTERFACE

input   [31:0]   wb_data_i;

input   [31:0]   wb_data_i;

output  [31:0]   wb_data_o;

output  [31:0]   wb_data_o;

Line 81...

Line 87...

output          wb_ack_o;

output          wb_ack_o;

output          wb_err_o;

output          wb_err_o;

// --------------------------------------

// --------------------------------------

// Misc Signals

// Misc Signals

output          int;

output          int_o;

output  [8:0]    dma_req;

output  [8:0]    dma_req_o;

input   [8:0]    dma_ack;

input   [8:0]    dma_ack_i;

// --------------------------------------

// --------------------------------------

// Suspend Resume Interface

// Suspend Resume Interface

output          suspended;

output          suspended_o;

// --------------------------------------

// --------------------------------------

// AC97 Codec Interface

// AC97 Codec Interface

input           bit_clk;

input           bit_clk_pad_i;

output          sync;

output          sync_pad_o;

output          sdata_out;

output          sdata_pad_o;

input           sdata_in;

input           sdata_pad_i;

output          ac97_reset_;

output          ac97_reset_pad_o_;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Local Wires

// Local Wires

//

//

Line 122...

Line 128...

wire    [19:0]   in_slt3;

wire    [19:0]   in_slt3;

wire    [19:0]   in_slt4;

wire    [19:0]   in_slt4;

wire    [19:0]   in_slt6;

wire    [19:0]   in_slt6;

// Serial IO Controller Interface

// Serial IO Controller Interface

wire            sync;

wire            ld;

wire            ld;

wire            valid;

wire            valid;

wire    [5:0]    out_le;

wire    [5:0]    out_le;

wire    [2:0]    in_valid;

wire    [2:0]    in_valid;

wire            ps_ce;

wire            ps_ce;

Line 157...

Line 162...

wire    [3:0]    adr;

wire    [3:0]    adr;

wire    [31:0]   rf_dout;

wire    [31:0]   rf_dout;

wire    [31:0]   rf_din;

wire    [31:0]   rf_din;

wire            rf_we;

wire            rf_we;

wire            rf_re;

wire            rf_re;

wire            int;

wire            ac97_rst_force;

wire            ac97_rst_force;

wire            resume_req;

wire            resume_req;

wire            crac_we;

wire            crac_we;

wire    [15:0]   crac_din;

wire    [15:0]   crac_din;

wire    [31:0]   crac_out;

wire    [31:0]   crac_out;

Line 193...

Line 197...

//

//

// Misc Logic

// Misc Logic

//

//

// Sync Valid to WISHBONE Clock

// Sync Valid to WISHBONE Clock

always @(posedge clk)

always @(posedge clk_i)

        valid_s1 <= #1 valid;

        valid_s1 <= #1 valid;

always @(posedge clk)

always @(posedge clk_i)

        valid_s <= #1 valid_s1;

        valid_s <= #1 valid_s1;

always @(posedge clk)

always @(posedge clk_i)

        in_valid_s1 <= #1 in_valid;

        in_valid_s1 <= #1 in_valid;

always @(posedge clk)

always @(posedge clk_i)

        in_valid_s <= #1 in_valid_s1;

        in_valid_s <= #1 in_valid_s1;

// "valid_s" Indicates when any of the outputs to the output S/R may

// "valid_s" Indicates when any of the outputs to the output S/R may

// change or when outputs from input S/R may be sampled

// change or when outputs from input S/R may be sampled

assign o3_mode = oc0_cfg[3:2];

assign o3_mode = oc0_cfg[3:2];

Line 223...

Line 227...

//

//

// Modules

// Modules

//

//

ac97_sout       u0(

ac97_sout       u0(

                .clk(           bit_clk         ),

                .clk(           bit_clk_pad_i   ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .so_ld(         ld              ),

                .so_ld(         ld              ),

                .slt0(          out_slt0        ),

                .slt0(          out_slt0        ),

                .slt1(          out_slt1        ),

                .slt1(          out_slt1        ),

                .slt2(          out_slt2        ),

                .slt2(          out_slt2        ),

                .slt3(          out_slt3        ),

                .slt3(          out_slt3        ),

                .slt4(          out_slt4        ),

                .slt4(          out_slt4        ),

                .slt6(          out_slt6        ),

                .slt6(          out_slt6        ),

                .slt7(          out_slt7        ),

                .slt7(          out_slt7        ),

                .slt8(          out_slt8        ),

                .slt8(          out_slt8        ),

                .slt9(          out_slt9        ),

                .slt9(          out_slt9        ),

                .sdata_out(     sdata_out       )

                .sdata_out(     sdata_pad_o     )

);

);

ac97_sin        u1(

ac97_sin        u1(

                .clk(           bit_clk         ),

                .clk(           bit_clk_pad_i   ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .out_le(        out_le          ),

                .out_le(        out_le          ),

                .slt0(          in_slt0         ),

                .slt0(          in_slt0         ),

                .slt1(          in_slt1         ),

                .slt1(          in_slt1         ),

                .slt2(          in_slt2         ),

                .slt2(          in_slt2         ),

                .slt3(          in_slt3         ),

                .slt3(          in_slt3         ),

                .slt4(          in_slt4         ),

                .slt4(          in_slt4         ),

                .slt6(          in_slt6         ),

                .slt6(          in_slt6         ),

                .sdata_in(      sdata_in        )

                .sdata_in(      sdata_pad_i     )

);

);

ac97_soc        u2(

ac97_soc        u2(

                .clk(           bit_clk         ),

                .clk(           bit_clk_pad_i   ),

                .wclk(          clk             ),

                .wclk(          clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .ps_ce(         ps_ce           ),

                .ps_ce(         ps_ce           ),

                .resume(        resume_req      ),

                .resume(        resume_req      ),

                .suspended(     suspended       ),

                .suspended(     suspended_o     ),

                .sync(          sync            ),

                .sync(          sync_pad_o      ),

                .out_le(        out_le          ),

                .out_le(        out_le          ),

                .in_valid(      in_valid        ),

                .in_valid(      in_valid        ),

                .ld(            ld              ),

                .ld(            ld              ),

                .valid(         valid           )

                .valid(         valid           )

);

);

ac97_out_fifo   u3(

ac97_out_fifo   u3(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            oc0_cfg[0]       ),

                .en(            oc0_cfg[0]       ),

                .mode(          o3_mode         ),

                .mode(          o3_mode         ),

                .din(           wb_din          ),

                .din(           wb_din          ),

                .we(            o3_we           ),

                .we(            o3_we           ),

                .dout(          out_slt3        ),

                .dout(          out_slt3        ),

Line 280...

Line 284...

                .full(          o3_full         ),

                .full(          o3_full         ),

                .empty(         o3_empty        )

                .empty(         o3_empty        )

);

);

ac97_out_fifo   u4(

ac97_out_fifo   u4(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            oc1_cfg[0]       ),

                .en(            oc1_cfg[0]       ),

                .mode(          o4_mode         ),

                .mode(          o4_mode         ),

                .din(           wb_din          ),

                .din(           wb_din          ),

                .we(            o4_we           ),

                .we(            o4_we           ),

                .dout(          out_slt4        ),

                .dout(          out_slt4        ),

Line 293...

Line 297...

                .status(        o4_status       ),

                .status(        o4_status       ),

                .full(          o4_full         ),

                .full(          o4_full         ),

                .empty(         o4_empty        )

                .empty(         o4_empty        )

);

);

`ifdef CENTER

`ifdef AC97_CENTER

ac97_out_fifo   u5(

ac97_out_fifo   u5(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            oc2_cfg[0]       ),

                .en(            oc2_cfg[0]       ),

                .mode(          o6_mode         ),

                .mode(          o6_mode         ),

                .din(           wb_din          ),

                .din(           wb_din          ),

                .we(            o6_we           ),

                .we(            o6_we           ),

                .dout(          out_slt6        ),

                .dout(          out_slt6        ),

Line 314...

Line 318...

assign o6_status = 0;

assign o6_status = 0;

assign o6_full = 0;

assign o6_full = 0;

assign o6_empty = 0;

assign o6_empty = 0;

`endif

`endif

`ifdef SURROUND

`ifdef AC97_SURROUND

ac97_out_fifo   u6(

ac97_out_fifo   u6(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            oc3_cfg[0]       ),

                .en(            oc3_cfg[0]       ),

                .mode(          o7_mode         ),

                .mode(          o7_mode         ),

                .din(           wb_din          ),

                .din(           wb_din          ),

                .we(            o7_we           ),

                .we(            o7_we           ),

                .dout(          out_slt7        ),

                .dout(          out_slt7        ),

Line 330...

Line 334...

                .full(          o7_full         ),

                .full(          o7_full         ),

                .empty(         o7_empty        )

                .empty(         o7_empty        )

);

);

ac97_out_fifo   u7(

ac97_out_fifo   u7(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            oc4_cfg[0]       ),

                .en(            oc4_cfg[0]       ),

                .mode(          o8_mode         ),

                .mode(          o8_mode         ),

                .din(           wb_din          ),

                .din(           wb_din          ),

                .we(            o8_we           ),

                .we(            o8_we           ),

                .dout(          out_slt8        ),

                .dout(          out_slt8        ),

Line 353...

Line 357...

assign o8_status = 0;

assign o8_status = 0;

assign o8_full = 0;

assign o8_full = 0;

assign o8_empty = 0;

assign o8_empty = 0;

`endif

`endif

`ifdef LFE

`ifdef AC97_LFE

ac97_out_fifo   u8(

ac97_out_fifo   u8(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            oc5_cfg[0]       ),

                .en(            oc5_cfg[0]       ),

                .mode(          o9_mode         ),

                .mode(          o9_mode         ),

                .din(           wb_din          ),

                .din(           wb_din          ),

                .we(            o9_we           ),

                .we(            o9_we           ),

                .dout(          out_slt9        ),

                .dout(          out_slt9        ),

Line 374...

Line 378...

assign o9_status = 0;

assign o9_status = 0;

assign o9_full = 0;

assign o9_full = 0;

assign o9_empty = 0;

assign o9_empty = 0;

`endif

`endif

`ifdef SIN

`ifdef AC97_SIN

ac97_in_fifo    u9(

ac97_in_fifo    u9(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            ic0_cfg[0]       ),

                .en(            ic0_cfg[0]       ),

                .mode(          i3_mode         ),

                .mode(          i3_mode         ),

                .din(           in_slt3         ),

                .din(           in_slt3         ),

                .we(            i3_we           ),

                .we(            i3_we           ),

                .dout(          i3_dout         ),

                .dout(          i3_dout         ),

Line 390...

Line 394...

                .full(          i3_full         ),

                .full(          i3_full         ),

                .empty(         i3_empty        )

                .empty(         i3_empty        )

);

);

ac97_in_fifo    u10(

ac97_in_fifo    u10(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            ic1_cfg[0]       ),

                .en(            ic1_cfg[0]       ),

                .mode(          i4_mode         ),

                .mode(          i4_mode         ),

                .din(           in_slt4         ),

                .din(           in_slt4         ),

                .we(            i4_we           ),

                .we(            i4_we           ),

                .dout(          i4_dout         ),

                .dout(          i4_dout         ),

Line 413...

Line 417...

assign i4_status = 0;

assign i4_status = 0;

assign i4_full = 0;

assign i4_full = 0;

assign i4_empty = 0;

assign i4_empty = 0;

`endif

`endif

`ifdef MICIN

`ifdef AC97_MICIN

ac97_in_fifo    u11(

ac97_in_fifo    u11(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .en(            ic2_cfg[0]       ),

                .en(            ic2_cfg[0]       ),

                .mode(          i6_mode         ),

                .mode(          i6_mode         ),

                .din(           in_slt6         ),

                .din(           in_slt6         ),

                .we(            i6_we           ),

                .we(            i6_we           ),

                .dout(          i6_dout         ),

                .dout(          i6_dout         ),

Line 435...

Line 439...

assign i6_full = 0;

assign i6_full = 0;

assign i6_empty = 0;

assign i6_empty = 0;

`endif

`endif

ac97_wb_if      u12(

ac97_wb_if      u12(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .wb_data_i(     wb_data_i       ),

                .wb_data_i(     wb_data_i       ),

                .wb_data_o(     wb_data_o       ),

                .wb_data_o(     wb_data_o       ),

                .wb_addr_i(     wb_addr_i       ),

                .wb_addr_i(     wb_addr_i       ),

                .wb_sel_i(      wb_sel_i        ),

                .wb_sel_i(      wb_sel_i        ),

                .wb_we_i(       wb_we_i         ),

                .wb_we_i(       wb_we_i         ),

Line 465...

Line 469...

                .i3_re(         i3_re           ),

                .i3_re(         i3_re           ),

                .i4_re(         i4_re           ),

                .i4_re(         i4_re           ),

                .i6_re(         i6_re           )

                .i6_re(         i6_re           )

);

);

ac97_rf u13(    .clk(           clk             ),

ac97_rf u13(    .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .adr(           adr             ),

                .adr(           adr             ),

                .rf_dout(       rf_dout         ),

                .rf_dout(       rf_dout         ),

                .rf_din(        wb_din          ),

                .rf_din(        wb_din          ),

                .rf_we(         rf_we           ),

                .rf_we(         rf_we           ),

                .rf_re(         rf_re           ),

                .rf_re(         rf_re           ),

                .int(           int             ),

                .int(           int_o           ),

                .ac97_rst_force(ac97_rst_force  ),

                .ac97_rst_force(ac97_rst_force  ),

                .resume_req(    resume_req      ),

                .resume_req(    resume_req      ),

                .suspended(     suspended       ),

                .suspended(     suspended_o     ),

                .crac_we(       crac_we         ),

                .crac_we(       crac_we         ),

                .crac_din(      crac_din        ),

                .crac_din(      crac_din        ),

                .crac_out(      crac_out        ),

                .crac_out(      crac_out        ),

                .crac_wr_done(  crac_wr_done    ),

                .crac_wr_done(  crac_wr_done    ),

                .crac_rd_done(  crac_rd_done    ),

                .crac_rd_done(  crac_rd_done    ),

Line 501...

Line 505...

                .ic0_int_set(   ic0_int_set     ),

                .ic0_int_set(   ic0_int_set     ),

                .ic1_int_set(   ic1_int_set     ),

                .ic1_int_set(   ic1_int_set     ),

                .ic2_int_set(   ic2_int_set     )

                .ic2_int_set(   ic2_int_set     )

);

);

ac97_prc u14(   .clk(           clk             ),

ac97_prc u14(   .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .valid(         valid_s         ),

                .valid(         valid_s         ),

                .in_valid(      in_valid_s      ),

                .in_valid(      in_valid_s      ),

                .out_slt0(      out_slt0        ),

                .out_slt0(      out_slt0        ),

                .in_slt0(       in_slt0         ),

                .in_slt0(       in_slt0         ),

                .in_slt1(       in_slt1         ),

                .in_slt1(       in_slt1         ),

Line 539...

Line 543...

                .i3_we(         i3_we           ),

                .i3_we(         i3_we           ),

                .i4_we(         i4_we           ),

                .i4_we(         i4_we           ),

                .i6_we(         i6_we           )

                .i6_we(         i6_we           )

);

);

ac97_cra u15(   .clk(           clk             ),

ac97_cra u15(   .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .crac_we(       crac_we         ),

                .crac_we(       crac_we         ),

                .crac_din(      crac_din        ),

                .crac_din(      crac_din        ),

                .crac_out(      crac_out        ),

                .crac_out(      crac_out        ),

                .crac_wr_done(  crac_wr_done    ),

                .crac_wr_done(  crac_wr_done    ),

                .crac_rd_done(  crac_rd_done    ),

                .crac_rd_done(  crac_rd_done    ),

Line 554...

Line 558...

                .in_slt2(       in_slt2         ),

                .in_slt2(       in_slt2         ),

                .crac_valid(    crac_valid      ),

                .crac_valid(    crac_valid      ),

                .crac_wr(       crac_wr         )

                .crac_wr(       crac_wr         )

);

);

ac97_dma_if u16(.clk(           clk             ),

ac97_dma_if u16(.clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .o3_status(     o3_status       ),

                .o3_status(     o3_status       ),

                .o4_status(     o4_status       ),

                .o4_status(     o4_status       ),

                .o6_status(     o6_status       ),

                .o6_status(     o6_status       ),

                .o7_status(     o7_status       ),

                .o7_status(     o7_status       ),

                .o8_status(     o8_status       ),

                .o8_status(     o8_status       ),

Line 583...

Line 587...

                .oc4_cfg(       oc4_cfg         ),

                .oc4_cfg(       oc4_cfg         ),

                .oc5_cfg(       oc5_cfg         ),

                .oc5_cfg(       oc5_cfg         ),

                .ic0_cfg(       ic0_cfg         ),

                .ic0_cfg(       ic0_cfg         ),

                .ic1_cfg(       ic1_cfg         ),

                .ic1_cfg(       ic1_cfg         ),

                .ic2_cfg(       ic2_cfg         ),

                .ic2_cfg(       ic2_cfg         ),

                .dma_req(       dma_req         ),

                .dma_req(       dma_req_o       ),

                .dma_ack(       dma_ack         )

                .dma_ack(       dma_ack_i       )

);

);

ac97_int        u17(

ac97_int        u17(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       oc0_int_set     ),

                .int_set(       oc0_int_set     ),

                .cfg(           oc0_cfg         ),

                .cfg(           oc0_cfg         ),

                .status(        o3_status       ),

                .status(        o3_status       ),

                .full_empty(    o3_empty        ),

                .full_empty(    o3_empty        ),

                .full(          o3_full         ),

                .full(          o3_full         ),

Line 601...

Line 605...

                .re(            o3_re           ),

                .re(            o3_re           ),

                .we(            o3_we           )

                .we(            o3_we           )

);

);

ac97_int        u18(

ac97_int        u18(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       oc1_int_set     ),

                .int_set(       oc1_int_set     ),

                .cfg(           oc1_cfg         ),

                .cfg(           oc1_cfg         ),

                .status(        o4_status       ),

                .status(        o4_status       ),

                .full_empty(    o4_empty        ),

                .full_empty(    o4_empty        ),

                .full(          o4_full         ),

                .full(          o4_full         ),

                .empty(         o4_empty        ),

                .empty(         o4_empty        ),

                .re(            o4_re           ),

                .re(            o4_re           ),

                .we(            o4_we           )

                .we(            o4_we           )

);

);

`ifdef CENTER

`ifdef AC97_CENTER

ac97_int        u19(

ac97_int        u19(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       oc2_int_set     ),

                .int_set(       oc2_int_set     ),

                .cfg(           oc2_cfg         ),

                .cfg(           oc2_cfg         ),

                .status(        o6_status       ),

                .status(        o6_status       ),

                .full_empty(    o6_empty        ),

                .full_empty(    o6_empty        ),

                .full(          o6_full         ),

                .full(          o6_full         ),

Line 630...

Line 634...

);

);

`else

`else

assign oc2_int_set = 0;

assign oc2_int_set = 0;

`endif

`endif

`ifdef SURROUND

`ifdef AC97_SURROUND

ac97_int        u20(

ac97_int        u20(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       oc3_int_set     ),

                .int_set(       oc3_int_set     ),

                .cfg(           oc3_cfg         ),

                .cfg(           oc3_cfg         ),

                .status(        o7_status       ),

                .status(        o7_status       ),

                .full_empty(    o7_empty        ),

                .full_empty(    o7_empty        ),

                .full(          o7_full         ),

                .full(          o7_full         ),

Line 645...

Line 649...

                .re(            o7_re           ),

                .re(            o7_re           ),

                .we(            o7_we           )

                .we(            o7_we           )

);

);

ac97_int        u21(

ac97_int        u21(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       oc4_int_set     ),

                .int_set(       oc4_int_set     ),

                .cfg(           oc4_cfg         ),

                .cfg(           oc4_cfg         ),

                .status(        o8_status       ),

                .status(        o8_status       ),

                .full_empty(    o8_empty        ),

                .full_empty(    o8_empty        ),

                .full(          o8_full         ),

                .full(          o8_full         ),

Line 661...

Line 665...

`else

`else

assign oc3_int_set = 0;

assign oc3_int_set = 0;

assign oc4_int_set = 0;

assign oc4_int_set = 0;

`endif

`endif

`ifdef LFE

`ifdef AC97_LFE

ac97_int        u22(

ac97_int        u22(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       oc5_int_set     ),

                .int_set(       oc5_int_set     ),

                .cfg(           oc5_cfg         ),

                .cfg(           oc5_cfg         ),

                .status(        o9_status       ),

                .status(        o9_status       ),

                .full_empty(    o9_empty        ),

                .full_empty(    o9_empty        ),

                .full(          o9_full         ),

                .full(          o9_full         ),

Line 678...

Line 682...

);

);

`else

`else

assign oc5_int_set = 0;

assign oc5_int_set = 0;

`endif

`endif

`ifdef SIN

`ifdef AC97_SIN

ac97_int        u23(

ac97_int        u23(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       ic0_int_set     ),

                .int_set(       ic0_int_set     ),

                .cfg(           ic0_cfg         ),

                .cfg(           ic0_cfg         ),

                .status(        i3_status       ),

                .status(        i3_status       ),

                .full_empty(    i3_full         ),

                .full_empty(    i3_full         ),

                .full(          i3_full         ),

                .full(          i3_full         ),

Line 693...

Line 697...

                .re(            i3_re           ),

                .re(            i3_re           ),

                .we(            i3_we           )

                .we(            i3_we           )

);

);

ac97_int        u24(

ac97_int        u24(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       ic1_int_set     ),

                .int_set(       ic1_int_set     ),

                .cfg(           ic1_cfg         ),

                .cfg(           ic1_cfg         ),

                .status(        i4_status       ),

                .status(        i4_status       ),

                .full_empty(    i4_full         ),

                .full_empty(    i4_full         ),

                .full(          i4_full         ),

                .full(          i4_full         ),

Line 709...

Line 713...

`else

`else

assign ic0_int_set = 0;

assign ic0_int_set = 0;

assign ic1_int_set = 0;

assign ic1_int_set = 0;

`endif

`endif

`ifdef MICIN

`ifdef AC97_MICIN

ac97_int        u25(

ac97_int        u25(

                .clk(           clk             ),

                .clk(           clk_i           ),

                .rst(           rst             ),

                .rst(           rst_i           ),

                .int_set(       ic2_int_set     ),

                .int_set(       ic2_int_set     ),

                .cfg(           ic2_cfg         ),

                .cfg(           ic2_cfg         ),

                .status(        i6_status       ),

                .status(        i6_status       ),

                .full_empty(    i6_full         ),

                .full_empty(    i6_full         ),

                .full(          i6_full         ),

                .full(          i6_full         ),

Line 727...

Line 731...

`else

`else

assign ic2_int_set = 0;

assign ic2_int_set = 0;

`endif

`endif

ac97_rst        u26(

ac97_rst        u26(

                .clk(           clk                             ),

                .clk(           clk_i                           ),

                .rst(           rst                             ),

                .rst(           rst_i                           ),

                .rst_force(     ac97_rst_force                  ),

                .rst_force(     ac97_rst_force                  ),

                .ps_ce(         ps_ce                           ),

                .ps_ce(         ps_ce                           ),

                .ac97_rst_(     ac97_reset_                     )

                .ac97_rst_(     ac97_reset_pad_o_               )

);

);

endmodule

endmodule

 No newline at end of file

 No newline at end of file

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_top.v] - Diff between revs 4 and 6