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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: ac97_wb_if.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
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// $Id: ac97_wb_if.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
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//
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//
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// $Date: 2001-08-10 08:09:42 $
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// $Date: 2002-03-05 04:44:05 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/10 08:09:42 rudi
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//
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// - Removed RTY_O output.
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// - Added Clock and Reset Inputs to documentation.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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//
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// Revision 1.1 2001/08/03 06:54:50 rudi
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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//
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//
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// - Changed to new directory structure
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// - Changed to new directory structure
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//
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//
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// Modules
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// Modules
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//
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//
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assign adr = wb_addr_i[5:2];
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assign adr = wb_addr_i[5:2];
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assign wb_err_o = 0;
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assign wb_err_o = 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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dout <= #1 wb_data_i;
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dout <= #1 wb_data_i;
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always @(posedge clk)
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always @(posedge clk)
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case(wb_addr_i[6:2]) // synopsys parallel_case full_case
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case(wb_addr_i[6:2]) // synopsys parallel_case full_case
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14: wb_data_o <= #1 i3_din;
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5'he: wb_data_o <= #1 i3_din;
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15: wb_data_o <= #1 i4_din;
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5'hf: wb_data_o <= #1 i4_din;
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16: wb_data_o <= #1 i6_din;
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5'h10: wb_data_o <= #1 i6_din;
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default: wb_data_o <= #1 rf_din;
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default: wb_data_o <= #1 rf_din;
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL;
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re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL;
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always @(posedge clk)
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always @(posedge clk)
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re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ;
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re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ;
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assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
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assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
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assign rf_re = re & (wb_addr_i[6:2] < 8);
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assign rf_re = re & (wb_addr_i[6:2] < 5'h8);
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always @(posedge clk)
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always @(posedge clk)
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we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
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we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
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always @(posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
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wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
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always @(posedge clk)
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always @(posedge clk)
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rf_we <= #1 we & (wb_addr_i[6:2] < 8);
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rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8);
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always @(posedge clk)
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always @(posedge clk)
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o3_we <= #1 we & (wb_addr_i[6:2] == 8);
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o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8);
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always @(posedge clk)
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always @(posedge clk)
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o4_we <= #1 we & (wb_addr_i[6:2] == 9);
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o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9);
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always @(posedge clk)
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always @(posedge clk)
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o6_we <= #1 we & (wb_addr_i[6:2] == 10);
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o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha);
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always @(posedge clk)
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always @(posedge clk)
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o7_we <= #1 we & (wb_addr_i[6:2] == 11);
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o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb);
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always @(posedge clk)
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always @(posedge clk)
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o8_we <= #1 we & (wb_addr_i[6:2] == 12);
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o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc);
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always @(posedge clk)
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always @(posedge clk)
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o9_we <= #1 we & (wb_addr_i[6:2] == 13);
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o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd);
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always @(posedge clk)
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always @(posedge clk)
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i3_re <= #1 re & (wb_addr_i[6:2] == 14);
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i3_re <= #1 re & (wb_addr_i[6:2] == 5'he);
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always @(posedge clk)
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always @(posedge clk)
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i4_re <= #1 re & (wb_addr_i[6:2] == 15);
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i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf);
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always @(posedge clk)
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always @(posedge clk)
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i6_re <= #1 re & (wb_addr_i[6:2] == 16);
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i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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