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1README_testbench.txt
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README_testbench.txt
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Advanced Debug Module (adv_dbg_if)
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Advanced Debug Module (adv_dbg_if)
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Nathan Yawn, nathan.yawn@opencores.org
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Nathan Yawn, nathan.yawn@opencores.org
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Two testbenches are supplied with the advanced debug interface. The first
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Two testbenches are supplied with the advanced debug interface. The first
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uses behavioral simulation of a wishbone bus with a memory attached, and
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uses behavioral simulation of a wishbone bus with a memory attached, and
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another behavioral simulatioin of an OR1200 CPU. This testbench performs
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another behavioral simulation of an OR1200 CPU. This testbench performs
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and tests bus / memory operations, and performs a few CPU operations, The
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and tests bus / memory operations, and performs a few CPU operations, The
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top-level module is in adv_dbg_tb.v. Other than the beavioral models, it
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top-level module is in adv_dbg_tb.v. Other than the beavioral models, it
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instantiates an adv_dbg_if (found in ../rtl/verilog/), and a JTAG TAP
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instantiates an adv_dbg_if (found in ../rtl/verilog/), and a JTAG TAP
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("jtag" module, not included with this module). Note that the TAP
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("jtag" module, not included with this module). Note that the TAP
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distributed by OpenCores will not work correctly; use the version modified
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distributed by OpenCores will not work correctly; use the version modified
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the JTAG TAP. This testbench is less polished, but includes a functional
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the JTAG TAP. This testbench is less polished, but includes a functional
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test of the single-step capability of the CPU.
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test of the single-step capability of the CPU.
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Both testbenches were written for use in ModelSim (version 6.3). A
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Both testbenches were written for use in ModelSim (version 6.3). A
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wave.do file is also included for each testbench, which will display a
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wave.do file is also included for each testbench, which will display a
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useful collectino of signals in the ModelSim wave view.
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useful collection of signals in the ModelSim wave view.
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