| Line 38... |
Line 38... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: adv_dbg_tb.v,v $
|
// $Log: adv_dbg_tb.v,v $
|
|
// Revision 1.6 2010-01-16 02:15:22 Nathan
|
|
// Updated to match changes in hardware. Added support for hi-speed mode.
|
|
//
|
|
// Revision 1.5 2010-01-08 01:41:07 Nathan
|
|
// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
|
|
//
|
// Revision 1.4 2009/05/17 20:54:55 Nathan
|
// Revision 1.4 2009/05/17 20:54:55 Nathan
|
// Changed email address to opencores.org
|
// Changed email address to opencores.org
|
//
|
//
|
// Revision 1.3 2008/07/11 08:18:47 Nathan
|
// Revision 1.3 2008/07/11 08:18:47 Nathan
|
// Added a bit to the CPU test. Added the hack that allows the driver to work with a Xilinx BSCAN device.
|
// Added a bit to the CPU test. Added the hack that allows the driver to work with a Xilinx BSCAN device.
|
//
|
//
|
|
|
|
|
`include "tap_defines.v"
|
`include "tap_defines.v"
|
`include "dbg_defines.v"
|
`include "adbg_defines.v"
|
`include "dbg_wb_defines.v"
|
`include "adbg_wb_defines.v"
|
|
|
|
|
// Polynomial for the CRC calculation
|
// Polynomial for the CRC calculation
|
// Yes, it's backwards. Yes, this is on purpose.
|
// Yes, it's backwards. Yes, this is on purpose.
|
// To decrease logic + routing, we want to shift the CRC calculation
|
// To decrease logic + routing, we want to shift the CRC calculation
|
| Line 617... |
Line 623... |
// Get us back to shift_dr mode to read a burst
|
// Get us back to shift_dr mode to read a burst
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(`JTAG_TMS_bit); // select_dr_scan
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // capture_ir
|
write_bit(3'h0); // shift_ir
|
write_bit(3'h0); // shift_ir
|
|
|
|
`ifdef ADBG_USE_HISPEED
|
|
// Get 1 status bit, then word_size_bytes*8 bits
|
|
status = 1'b0;
|
|
j = 0;
|
|
while(!status) begin
|
|
read_write_bit(3'h0, status);
|
|
j = j + 1;
|
|
end
|
|
|
|
if(j > 1) begin
|
|
$display("Took %0d tries before good status bit during burst read", j);
|
|
end
|
|
`endif
|
|
|
// Now, repeat...
|
// Now, repeat...
|
for(i = 0; i < word_count; i=i+1) begin
|
for(i = 0; i < word_count; i=i+1) begin
|
|
|
|
`ifndef ADBG_USE_HISPEED
|
// Get 1 status bit, then word_size_bytes*8 bits
|
// Get 1 status bit, then word_size_bytes*8 bits
|
status = 1'b0;
|
status = 1'b0;
|
j = 0;
|
j = 0;
|
while(!status) begin
|
while(!status) begin
|
read_write_bit(3'h0, status);
|
read_write_bit(3'h0, status);
|
| Line 630... |
Line 652... |
end
|
end
|
|
|
if(j > 1) begin
|
if(j > 1) begin
|
$display("Took %0d tries before good status bit during burst read", j);
|
$display("Took %0d tries before good status bit during burst read", j);
|
end
|
end
|
|
`endif
|
|
|
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
|
jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
|
//$display("Read 0x%0x", instream[31:0]);
|
//$display("Read 0x%0x", instream[31:0]);
|
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
|
compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
|
crc_calc_i = crc_calc_o;
|
crc_calc_i = crc_calc_o;
|
| Line 707... |
Line 730... |
|
|
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
|
jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
|
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
|
compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
|
crc_calc_i = crc_calc_o;
|
crc_calc_i = crc_calc_o;
|
|
|
|
`ifndef ADBG_USE_HISPEED
|
// Check if WB bus is ready
|
// Check if WB bus is ready
|
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
|
// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
|
status = 1'b0;
|
status = 1'b0;
|
read_write_bit(3'h0, status);
|
read_write_bit(3'h0, status);
|
|
|
if(!status) begin
|
if(!status) begin
|
$display("Bad status bit during burst write, index %d", i);
|
$display("Bad status bit during burst write, index %d", i);
|
end
|
end
|
|
`endif
|
|
|
//$display("Wrote 0x%0x", dataword);
|
//$display("Wrote 0x%0x", dataword);
|
end
|
end
|
|
|
// Send the CRC we computed
|
// Send the CRC we computed
|
