URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [bench/] [full_system/] [xsv_fpga_defines.v] - Diff between revs 8 and 32

Rev 8	Rev 32
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: xsv_fpga_defines.v,v $`	`// $Log: xsv_fpga_defines.v,v $`
	`// Revision 1.3 2010-01-08 01:41:07 Nathan`
	`// Removed unused, non-existant include from CPU behavioral model. Minor text edits.`
	`//`
`// Revision 1.2 2008/07/11 08:16:01 Nathan`	`// Revision 1.2 2008/07/11 08:16:01 Nathan`
`// Ran through dos2unix`	`// Ran through dos2unix`
`//`	`//`
`// Revision 1.1 2008/07/08 19:11:54 Nathan`	`// Revision 1.1 2008/07/08 19:11:54 Nathan`
`// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.`	`// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.`