| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: xsv_fpga_top.v,v $
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// $Log: xsv_fpga_top.v,v $
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// Revision 1.5 2010-01-16 02:15:22 Nathan
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// Updated to match changes in hardware. Added support for hi-speed mode.
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//
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// Revision 1.4 2010-01-08 01:41:07 Nathan
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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//
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// Revision 1.3 2008/07/11 08:22:17 Nathan
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// Revision 1.3 2008/07/11 08:22:17 Nathan
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// Added code to make the native TAP simulate a Xilinx BSCAN device, and code to simulate the behavior of the xilinx_internal_jtag module. The adv_dbg_module should get inputs that emulate the xilinx_internal_jtag device outputs.
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// Added code to make the native TAP simulate a Xilinx BSCAN device, and code to simulate the behavior of the xilinx_internal_jtag module. The adv_dbg_module should get inputs that emulate the xilinx_internal_jtag device outputs.
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//
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//
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// Revision 1.10 2004/04/05 08:44:35 lampret
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// Revision 1.10 2004/04/05 08:44:35 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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| Line 394... |
Line 400... |
.sample_preload_select_o(),
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.sample_preload_select_o(),
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.mbist_select_o(),
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.mbist_select_o(),
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.debug_select_o(debug_select),
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.debug_select_o(debug_select),
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// TDO signal that is connected to TDI of sub-modules.
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// TDO signal that is connected to TDI of sub-modules.
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.tdo_o(debug_tdi),
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.tdi_o(debug_tdi),
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// TDI signals from sub-modules
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// TDI signals from sub-modules
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.debug_tdi_i(debug_tdo), // from debug module
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.debug_tdo_i(debug_tdo), // from debug module
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.bs_chain_tdi_i(1'b0), // from Boundary Scan Chain
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.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
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.mbist_tdi_i(1'b0) // from Mbist Chain
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.mbist_tdo_i(1'b0) // from Mbist Chain
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);
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);
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// This is taken from the xilinx bscan_virtex4.v module
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// This is taken from the xilinx bscan_virtex4.v module
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// It simulates the DRCK output of a BSCAN_* block
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// It simulates the DRCK output of a BSCAN_* block
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assign drck = ((debug_select & !shift_dr & !capture_dr) ||
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assign drck = ((debug_select & !shift_dr & !capture_dr) ||
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| Line 440... |
Line 446... |
end
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end
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//
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//
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// Instantiation of the development i/f
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// Instantiation of the development i/f
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//
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//
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dbg_top dbg_top (
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adbg_top dbg_top (
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// JTAG pins
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// JTAG pins
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.tck_i ( tck2 ),
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.tck_i ( tck2 ),
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.tdi_i ( debug_tdi ),
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.tdi_i ( debug_tdi ),
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.tdo_o ( debug_tdo ),
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.tdo_o ( debug_tdo ),
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