| Line 38... |
Line 38... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adv_dbg_tb.v,v $
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// $Log: adv_dbg_tb.v,v $
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// Revision 1.7 2010-01-13 00:55:45 Nathan
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// Created hi-speed mode for burst reads. This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
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//
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// Revision 1.2 2009/05/17 20:54:55 Nathan
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// Revision 1.2 2009/05/17 20:54:55 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/08 19:11:55 Nathan
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// Revision 1.1 2008/07/08 19:11:55 Nathan
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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| Line 53... |
Line 56... |
// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver.
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// Removed code to select top-level module as active (it served no purpose). Re-numbered modules, requiring changes to testbench and software driver.
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//
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//
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`include "tap_defines.v"
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`include "tap_defines.v"
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`include "dbg_defines.v"
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`include "adbg_defines.v"
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`include "dbg_wb_defines.v"
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`include "adbg_wb_defines.v"
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`include "wb_model_defines.v"
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`include "wb_model_defines.v"
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// Polynomial for the CRC calculation
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// Polynomial for the CRC calculation
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// Yes, it's backwards. Yes, this is on purpose.
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// Yes, it's backwards. Yes, this is on purpose.
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// To decrease logic + routing, we want to shift the CRC calculation
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// To decrease logic + routing, we want to shift the CRC calculation
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| Line 303... |
Line 306... |
write_bit(`JTAG_TMS_bit); // update_dr
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write_bit(`JTAG_TMS_bit); // update_dr
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write_bit(3'h0); // idle
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write_bit(3'h0); // idle
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#1000;
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#1000;
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*/
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*/
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#1000;
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/*
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$display("Testing WB intreg select at time %t", $time);
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#1000;
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select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
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$display("Testing WB intreg select at time %t", $time);
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#1000;
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select_module_internal_register(32'h1, 1); // Really just a read, with discarded data
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select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
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#1000;
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#1000;
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select_module_internal_register(32'h0, 1); // Really just a read, with discarded data
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#1000;
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// Reset the error bit
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write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
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#1000;
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// Read the error bit
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// Reset the error bit
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read_module_internal_register(8'd33, err_data); // We assume the register is already selected
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write_module_internal_register(32'h0, 8'h1, 32'h1, 8'h1); // idx, idxlen, data, datalen
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#1000;
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#1000;
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// Read the error bit
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read_module_internal_register(8'd33, err_data); // We assume the register is already selected
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#1000;
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*/
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/////////////////////////////////
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/////////////////////////////////
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// Test 8-bit WB access
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// Test 8-bit WB access
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failed = 0;
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failed = 0;
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$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
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$display("Testing WB 8-bit burst write at time %t: resetting ", $time);
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| Line 449... |
Line 453... |
.sample_preload_select_o(),
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.sample_preload_select_o(),
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.mbist_select_o(),
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.mbist_select_o(),
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.debug_select_o(dbg_sel),
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.debug_select_o(dbg_sel),
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// TDO signal that is connected to TDI of sub-modules.
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// TDO signal that is connected to TDI of sub-modules.
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.tdo_o(dbg_tdo),
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.tdi_o(dbg_tdo),
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// TDI signals from sub-modules
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// TDI signals from sub-modules
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.debug_tdi_i(dbg_tdi), // from debug module
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.debug_tdo_i(dbg_tdi), // from debug module
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.bs_chain_tdi_i(1'b0), // from Boundary Scan Chain
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.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
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.mbist_tdi_i(1'b0) // from Mbist Chain
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.mbist_tdo_i(1'b0) // from Mbist Chain
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);
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);
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// Top module
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// Top module
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dbg_top i_dbg_module(
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adbg_top i_dbg_module(
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// JTAG signals
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// JTAG signals
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.tck_i(jtag_tck_o),
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.tck_i(jtag_tck_o),
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.tdi_i(dbg_tdo),
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.tdi_i(dbg_tdo),
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.tdo_o(dbg_tdi),
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.tdo_o(dbg_tdi),
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.rst_i(dbg_rst),
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.rst_i(dbg_rst),
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| Line 790... |
Line 794... |
// Get us back to shift_dr mode to read a burst
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// Get us back to shift_dr mode to read a burst
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write_bit(`JTAG_TMS_bit); // select_dr_scan
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write_bit(`JTAG_TMS_bit); // select_dr_scan
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write_bit(3'h0); // capture_ir
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write_bit(3'h0); // capture_ir
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write_bit(3'h0); // shift_ir
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write_bit(3'h0); // shift_ir
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`ifdef ADBG_USE_HISPEED
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// Get 1 status bit, then word_size_bytes*8 bits
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status = 1'b0;
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j = 0;
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while(!status) begin
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read_write_bit(3'h0, status);
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j = j + 1;
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end
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if(j > 1) begin
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$display("Took %0d tries before good status bit during burst read", j);
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end
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`endif
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// Now, repeat...
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// Now, repeat...
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for(i = 0; i < word_count; i=i+1) begin
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for(i = 0; i < word_count; i=i+1) begin
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`ifndef ADBG_USE_HISPEED
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// Get 1 status bit, then word_size_bytes*8 bits
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// Get 1 status bit, then word_size_bytes*8 bits
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status = 1'b0;
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status = 1'b0;
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j = 0;
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j = 0;
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while(!status) begin
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while(!status) begin
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read_write_bit(3'h0, status);
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read_write_bit(3'h0, status);
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| Line 803... |
Line 823... |
end
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end
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if(j > 1) begin
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if(j > 1) begin
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$display("Took %0d tries before good status bit during burst read", j);
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$display("Took %0d tries before good status bit during burst read", j);
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end
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end
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`endif
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jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
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jtag_read_write_stream(64'h0, {2'h0,(word_size_bytes<<3)},0,instream);
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//$display("Read 0x%0x", instream[31:0]);
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//$display("Read 0x%0x", instream[31:0]);
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compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
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compute_crc(crc_calc_i, instream[31:0], word_size_bits, crc_calc_o);
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crc_calc_i = crc_calc_o;
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crc_calc_i = crc_calc_o;
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| Line 880... |
Line 901... |
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jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
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jtag_write_stream(dataword, {2'h0,(word_size_bytes<<3)},0);
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compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
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compute_crc(crc_calc_i, dataword[31:0], word_size_bits, crc_calc_o);
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crc_calc_i = crc_calc_o;
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crc_calc_i = crc_calc_o;
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`ifndef ADBG_USE_HISPEED
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// Check if WB bus is ready
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// Check if WB bus is ready
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// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
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// *** THIS WILL NOT WORK IF THERE IS MORE THAN 1 DEVICE IN THE JTAG CHAIN!!!
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status = 1'b0;
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status = 1'b0;
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read_write_bit(3'h0, status);
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read_write_bit(3'h0, status);
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if(!status) begin
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if(!status) begin
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$display("Bad status bit during burst write, index %d", i);
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$display("Bad status bit during burst write, index %d", i);
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end
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end
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`endif
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//$display("Wrote 0x%0x", dataword);
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//$display("Wrote 0x%0x", dataword);
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end
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end
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// Send the CRC we computed
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// Send the CRC we computed
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