// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Revision 1.1 2008/07/08 19:11:55 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
//
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Revision 1.1 2008/06/18 18:34:48 Nathan
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.