// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
//
// Revision 1.1 2008/07/08 19:11:57 Nathan
// Revision 1.1 2008/07/08 19:11:57 Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
//
//
// Revision 1.2 2008/06/26 20:54:44 Nathan
// Revision 1.2 2008/06/26 20:54:44 Nathan
// Testbench modified to use WB behavioral model instead of an onchip_ram. Added test of WB error register.
// Testbench modified to use WB behavioral model instead of an onchip_ram. Added test of WB error register.