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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Authors ////
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//// Copyright (C) 2008 - 2010 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adbg_or1k_module.v,v $
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// $Log: adbg_or1k_module.v,v $
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// Revision 1.5 2010-01-13 00:55:45 Nathan
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// Created hi-speed mode for burst reads. This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
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//
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/22 20:28:31 Nathan
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// Revision 1.1 2008/07/22 20:28:31 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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Line 57... |
// to ignore the command present in the input shift register after e.g.
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// to ignore the command present in the input shift register after e.g.
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// a burst read.
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// a burst read.
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//
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//
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`include "adbg_defines.v"
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`include "adbg_or1k_defines.v"
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`include "adbg_or1k_defines.v"
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// Module interface
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// Module interface
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module adbg_or1k_module (
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module adbg_or1k_module (
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// JTAG signals
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// JTAG signals
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Line 193... |
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assign module_cmd = ~(data_register_i[52]);
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assign module_cmd = ~(data_register_i[52]);
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assign operation_in = data_register_i[51:48];
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assign operation_in = data_register_i[51:48];
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assign address_data_in = data_register_i[47:16];
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assign address_data_in = data_register_i[47:16];
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assign count_data_in = data_register_i[15:0];
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assign count_data_in = data_register_i[15:0];
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`ifdef ADBG_USE_HISPEED
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assign data_to_biu = {tdi_i,data_register_i[52:22]};
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`else
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assign data_to_biu = data_register_i[52:21];
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assign data_to_biu = data_register_i[52:21];
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`endif
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assign reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];
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assign reg_select_data = data_register_i[47:(47-(`DBG_OR1K_REGSELECT_SIZE-1))];
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////////////////////////////////////////////////
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////////////////////////////////////////////////
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// Operation decoder
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// Operation decoder
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Line 459... |
end
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end
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`STATE_Rburst:
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`STATE_Rburst:
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begin
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begin
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if(update_dr_i) module_next_state <= `STATE_idle;
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if(update_dr_i) module_next_state <= `STATE_idle;
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else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc;
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else if(bit_count_max && word_count_zero) module_next_state <= `STATE_Rcrc;
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`ifndef ADBG_USE_HISPEED
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else if(bit_count_max) module_next_state <= `STATE_Rstatus;
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else if(bit_count_max) module_next_state <= `STATE_Rstatus;
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`endif
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else module_next_state <= `STATE_Rburst;
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else module_next_state <= `STATE_Rburst;
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end
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end
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`STATE_Rcrc:
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`STATE_Rcrc:
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begin
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begin
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if(update_dr_i) module_next_state <= `STATE_idle;
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if(update_dr_i) module_next_state <= `STATE_idle;
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Line 486... |
else module_next_state <= `STATE_Wwait;
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else module_next_state <= `STATE_Wwait;
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end
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end
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`STATE_Wburst:
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`STATE_Wburst:
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begin
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begin
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if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
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if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
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else if(bit_count_max) module_next_state <= `STATE_Wstatus;
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else if(bit_count_max)
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begin
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`ifdef ADBG_USE_HISPEED
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if(word_count_zero) module_next_state <= `STATE_Wcrc;
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else module_next_state <= `STATE_Wburst;
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`else
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module_next_state <= `STATE_Wstatus;
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`endif
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end
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else module_next_state <= `STATE_Wburst;
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else module_next_state <= `STATE_Wburst;
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end
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end
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`STATE_Wstatus:
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`STATE_Wstatus:
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begin
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begin
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if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
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if(update_dr_i) module_next_state <= `STATE_idle; // client terminated early
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Line 597... |
`STATE_Rstatus:
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`STATE_Rstatus:
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begin
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begin
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tdo_output_sel <= 2'h0;
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tdo_output_sel <= 2'h0;
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top_inhibit_o <= 1'b1; // in case of early termination
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top_inhibit_o <= 1'b1; // in case of early termination
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if (module_next_state == `STATE_Rburst) begin
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if (module_next_state == `STATE_Rburst)
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begin
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out_reg_data_sel <= 1'b0; // select BIU data
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out_reg_data_sel <= 1'b0; // select BIU data
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out_reg_ld_en <= 1'b1;
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out_reg_ld_en <= 1'b1;
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bit_ct_rst <= 1'b1;
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bit_ct_rst <= 1'b1;
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word_ct_sel <= 1'b1;
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word_ct_sel <= 1'b1;
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word_ct_en <= 1'b1;
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word_ct_en <= 1'b1;
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if(!(decremented_word_count == 0) && !word_count_zero) begin // Start a biu read transaction
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if(!(decremented_word_count == 0) && !word_count_zero) // Start a biu read transaction
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begin
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biu_strobe <= 1'b1;
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biu_strobe <= 1'b1;
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addr_sel <= 1'b1;
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addr_sel <= 1'b1;
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addr_ct_en <= 1'b1;
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addr_ct_en <= 1'b1;
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end
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end
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end
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end
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Line 621... |
out_reg_shift_en <= 1'b1;
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out_reg_shift_en <= 1'b1;
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bit_ct_en <= 1'b1;
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bit_ct_en <= 1'b1;
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crc_en <= 1'b1;
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crc_en <= 1'b1;
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crc_in_sel <= 1'b0; // read data in output shift register LSB (tdo)
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crc_in_sel <= 1'b0; // read data in output shift register LSB (tdo)
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top_inhibit_o <= 1'b1; // in case of early termination
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top_inhibit_o <= 1'b1; // in case of early termination
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`ifdef ADBG_USE_HISPEED
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if(bit_count_max)
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begin
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out_reg_data_sel <= 1'b0; // select BIU data
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out_reg_ld_en <= 1'b1;
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bit_ct_rst <= 1'b1;
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word_ct_sel <= 1'b1;
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word_ct_en <= 1'b1;
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if(!(decremented_word_count == 0) && !word_count_zero) // Start a biu read transaction
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begin
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biu_strobe <= 1'b1;
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addr_sel <= 1'b1;
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addr_ct_en <= 1'b1;
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end
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end
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`endif
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end
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end
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`STATE_Rcrc:
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`STATE_Rcrc:
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begin
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begin
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// Just shift out the data, don't bother counting, we don't move on until update_dr_i
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// Just shift out the data, don't bother counting, we don't move on until update_dr_i
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Line 671... |
bit_ct_en <= 1'b1;
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bit_ct_en <= 1'b1;
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tdo_output_sel <= 2'h1;
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tdo_output_sel <= 2'h1;
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crc_en <= 1'b1;
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crc_en <= 1'b1;
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crc_in_sel <= 1'b1; // read data from tdi_i
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crc_in_sel <= 1'b1; // read data from tdi_i
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top_inhibit_o <= 1'b1; // in case of early termination
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top_inhibit_o <= 1'b1; // in case of early termination
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`ifdef ADBG_USE_HISPEED
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// It would be better to do this in STATE_Wstatus, but we don't use that state
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// if ADBG_USE_HISPEED is defined.
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if(bit_count_max)
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begin
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bit_ct_rst <= 1'b1; // Zero the bit count
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// start transaction. Can't do this here if not hispeed, biu_ready
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// is the status bit, and it's 0 if we start a transaction here.
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biu_strobe <= 1'b1; // Start a BIU transaction
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addr_ct_en <= 1'b1; // Increment thte address counter
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// Also can't dec the byte count yet unless hispeed,
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// that would skip the last word.
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word_ct_sel <= 1'b1; // Decrement the byte count
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word_ct_en <= 1'b1;
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end
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`endif
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end
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end
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`STATE_Wstatus:
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`STATE_Wstatus:
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begin
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begin
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tdo_output_sel <= 2'h0; // Send the status bit to TDO
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tdo_output_sel <= 2'h0; // Send the status bit to TDO
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