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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_status_reg.v] - Diff between revs 8 and 32

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Rev 8 Rev 32
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//// Copyright (C) 2000 - 2008 Authors                            ////
//// Copyright (C) 2000 - 2010 Authors                            ////
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//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
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//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: adbg_or1k_status_reg.v,v $
// $Log: adbg_or1k_status_reg.v,v $
 
// Revision 1.2  2010-01-10 22:54:10  Nathan
 
// Update copyright dates
 
//
// Revision 1.1  2008/07/22 20:28:31  Nathan
// Revision 1.1  2008/07/22 20:28:31  Nathan
// Changed names of all files and modules (prefixed an a, for advanced).  Cleanup, indenting.  No functional changes.
// Changed names of all files and modules (prefixed an a, for advanced).  Cleanup, indenting.  No functional changes.
//
//
// Revision 1.3  2008/07/06 20:02:54  Nathan
// Revision 1.3  2008/07/06 20:02:54  Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with 
// Fixes for synthesis with Xilinx ISE (also synthesizable with 

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