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Line 45... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: xilinx_internal_jtag.v,v $
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// $Log: xilinx_internal_jtag.v,v $
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// Revision 1.4 2009-12-28 01:15:28 Nathan
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// Removed incorrect duplicate assignment of capture_dr_o in SPARTAN2 TAP, per bug report from Raul Fajardo.
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//
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// Revision 1.3 2009/06/16 02:54:23 Nathan
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// Revision 1.3 2009/06/16 02:54:23 Nathan
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// Changed some signal names for better consistency between different hardware modules.
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// Changed some signal names for better consistency between different hardware modules.
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//
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//
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// Revision 1.2 2009/05/17 20:54:16 Nathan
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// Revision 1.2 2009/05/17 20:54:16 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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.TDO2( 1'b0 ) // Data input for USER2 function
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.TDO2( 1'b0 ) // Data input for USER2 function
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);
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);
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assign pause_dr_o = 1'b0;
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assign pause_dr_o = 1'b0;
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assign run_test_idle_o = 1'b0;
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assign run_test_idle_o = 1'b0;
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assign capture_dr_o = 1'b0;
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// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
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// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
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// On that negative edge, set capture_dr, and it will get registered on the rising
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// On that negative edge, set capture_dr, and it will get registered on the rising
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// edge.
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// edge.
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always @ (negedge tck_o)
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always @ (negedge tck_o)
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