| Line 157... |
Line 157... |
}
|
}
|
|
|
|
|
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
|
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(!len)
|
if(!len)
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
|
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
| Line 190... |
Line 190... |
|
|
|
|
// Never actually called from the GDB interface
|
// Never actually called from the GDB interface
|
int dbg_wb_read_block16(unsigned long adr, uint16_t *data, int len) {
|
int dbg_wb_read_block16(unsigned long adr, uint16_t *data, int len) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(!len)
|
if(!len)
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
|
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
| Line 222... |
Line 222... |
}
|
}
|
|
|
// Never actually called from the GDB interface
|
// Never actually called from the GDB interface
|
int dbg_wb_read_block8(unsigned long adr, uint8_t *data, int len) {
|
int dbg_wb_read_block8(unsigned long adr, uint8_t *data, int len) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(!len)
|
if(!len)
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
|
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
| Line 249... |
Line 249... |
pthread_mutex_unlock(&dbg_access_mutex);
|
pthread_mutex_unlock(&dbg_access_mutex);
|
return err;
|
return err;
|
}
|
}
|
|
|
|
|
|
|
// write a block to wishbone
|
// write a block to wishbone
|
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
|
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(!len)
|
if(!len)
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
|
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
| Line 287... |
Line 286... |
|
|
// write a block to wishbone
|
// write a block to wishbone
|
// Never actually called from the GDB interface
|
// Never actually called from the GDB interface
|
int dbg_wb_write_block16(unsigned long adr, uint16_t *data, int len) {
|
int dbg_wb_write_block16(unsigned long adr, uint16_t *data, int len) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(!len)
|
if(!len)
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
|
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
| Line 319... |
Line 318... |
}
|
}
|
|
|
// write a block to wishbone
|
// write a block to wishbone
|
int dbg_wb_write_block8(unsigned long adr, uint8_t *data, int len) {
|
int dbg_wb_write_block8(unsigned long adr, uint8_t *data, int len) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(!len)
|
if(!len)
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
|
|
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
if ((err = adbg_select_module(DC_WISHBONE)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
| Line 377... |
Line 376... |
}
|
}
|
|
|
/* read multiple registers from cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
|
/* read multiple registers from cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
|
int dbg_cpu0_read_block(unsigned long adr, unsigned long *data, int count) {
|
int dbg_cpu0_read_block(unsigned long adr, unsigned long *data, int count) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if ((err = adbg_select_module(DC_CPU0)))
|
if ((err = adbg_select_module(DC_CPU0)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
pthread_mutex_unlock(&dbg_access_mutex);
|
pthread_mutex_unlock(&dbg_access_mutex);
|
return err;
|
return err;
|
}
|
}
|
err = adbg_wb_burst_read(4, count, adr, (void *) data); // All CPU register reads / writes are bursts
|
err = adbg_wb_burst_read(4, count, adr, (void *) data); // All CPU register reads / writes are bursts
|
|
cable_flush();
|
|
pthread_mutex_unlock(&dbg_access_mutex);
|
}
|
}
|
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
|
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
|
{
|
{
|
int i;
|
int i;
|
unsigned long readaddr = adr;
|
unsigned long readaddr = adr;
|
err = APP_ERR_NONE;
|
err = APP_ERR_NONE;
|
for(i = 0; i < count; i++) {
|
for(i = 0; i < count; i++) {
|
err |= dbg_cpu0_read(readaddr++, &data[i]);
|
err |= dbg_cpu0_read(readaddr++, &data[i]);
|
}
|
}
|
}
|
}
|
cable_flush();
|
|
pthread_mutex_unlock(&dbg_access_mutex);
|
|
debug("dbg_cpu_read_block(), addr 0x%X, count %i, data[0] = 0x%X\n", adr, count, data[0]);
|
debug("dbg_cpu_read_block(), addr 0x%X, count %i, data[0] = 0x%X\n", adr, count, data[0]);
|
return err;
|
return err;
|
}
|
}
|
|
|
/* write a cpu register to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
|
/* write a cpu register to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
|
| Line 435... |
Line 435... |
}
|
}
|
|
|
/* write multiple cpu registers to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
|
/* write multiple cpu registers to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
|
int dbg_cpu0_write_block(unsigned long adr, unsigned long *data, int count) {
|
int dbg_cpu0_write_block(unsigned long adr, unsigned long *data, int count) {
|
int err;
|
int err;
|
pthread_mutex_lock(&dbg_access_mutex);
|
|
|
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
|
{
|
{
|
|
pthread_mutex_lock(&dbg_access_mutex);
|
if ((err = adbg_select_module(DC_CPU0)))
|
if ((err = adbg_select_module(DC_CPU0)))
|
{
|
{
|
cable_flush();
|
cable_flush();
|
pthread_mutex_unlock(&dbg_access_mutex);
|
pthread_mutex_unlock(&dbg_access_mutex);
|
return err;
|
return err;
|
}
|
}
|
err = adbg_wb_burst_write((void *)data, 4, count, adr);
|
err = adbg_wb_burst_write((void *)data, 4, count, adr);
|
|
cable_flush();
|
|
pthread_mutex_unlock(&dbg_access_mutex);
|
}
|
}
|
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
|
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
|
{
|
{
|
int i;
|
int i;
|
unsigned long writeaddr = adr;
|
unsigned long writeaddr = adr;
|
| Line 457... |
Line 459... |
for(i = 0; i < count; i++) {
|
for(i = 0; i < count; i++) {
|
err |= dbg_cpu0_write(writeaddr++, data[i]);
|
err |= dbg_cpu0_write(writeaddr++, data[i]);
|
}
|
}
|
}
|
}
|
debug("cpu0_write_block, adr 0x%X, data[0] 0x%X, count %i, ret %i\n", adr, data[0], count, err);
|
debug("cpu0_write_block, adr 0x%X, data[0] 0x%X, count %i, ret %i\n", adr, data[0], count, err);
|
cable_flush();
|
|
pthread_mutex_unlock(&dbg_access_mutex);
|
|
return err;
|
return err;
|
}
|
}
|
|
|
/* write a debug unit cpu module register
|
/* write a debug unit cpu module register
|
* Since OR32 debug module has only 1 register,
|
* Since OR32 debug module has only 1 register,
|
