| Line 7... |
Line 7... |
// Last Modified On: 2006-12-29
|
// Last Modified On: 2006-12-29
|
// Update Count : 0
|
// Update Count : 0
|
// Status : Beta/Stable
|
// Status : Beta/Stable
|
|
|
/*
|
/*
|
* $Id: ae18_core.v,v 1.4 2006-12-29 18:08:56 sybreon Exp $
|
* $Id: ae18_core.v,v 1.5 2007-03-04 23:26:37 sybreon Exp $
|
*
|
*
|
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
|
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
|
*
|
*
|
* This library is free software; you can redistribute it and/or modify it
|
* This library is free software; you can redistribute it and/or modify it
|
* under the terms of the GNU Lesser General Public License as published by
|
* under the terms of the GNU Lesser General Public License as published by
|
| Line 34... |
Line 34... |
* need to be integrated with the core. This core provides the necessary
|
* need to be integrated with the core. This core provides the necessary
|
* signals to wire up WISHBONE compatible devices to it.
|
* signals to wire up WISHBONE compatible devices to it.
|
*
|
*
|
* HISTORY
|
* HISTORY
|
* $Log: not supported by cvs2svn $
|
* $Log: not supported by cvs2svn $
|
|
* Revision 1.4 2006/12/29 18:08:56 sybreon
|
|
* Minor code clean up
|
|
*
|
*
|
*
|
*/
|
*/
|
|
|
module ae18_core (/*AUTOARG*/
|
module ae18_core (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
| Line 75... |
Line 78... |
// System
|
// System
|
input [1:0] int_i;
|
input [1:0] int_i;
|
input [7:6] inte_i;
|
input [7:6] inte_i;
|
input clk_i, rst_i;
|
input clk_i, rst_i;
|
|
|
|
/*
|
|
* Parameters
|
|
*/
|
|
// State Registers
|
|
parameter [2:0]
|
|
FSM_RUN = 4'h0,
|
|
FSM_ISRL = 4'h1,
|
|
FSM_ISRH = 4'h2,
|
|
FSM_SLEEP = 4'h3;
|
|
|
|
parameter [1:0]
|
|
FSM_Q0 = 2'h0,
|
|
FSM_Q1 = 2'h1,
|
|
FSM_Q2 = 2'h2,
|
|
FSM_Q3 = 2'h3;
|
|
|
|
// MX_SRC
|
|
parameter [1:0]
|
|
MXSRC_MASK = 2'h2,
|
|
MXSRC_LIT = 2'h3,
|
|
MXSRC_WREG = 2'h0,
|
|
MXSRC_FILE = 2'h1;
|
|
// MX_TGT
|
|
parameter [1:0]
|
|
MXTGT_MASK = 2'h2,
|
|
MXTGT_LIT = 2'h3,
|
|
MXTGT_WREG = 2'h0,
|
|
MXTGT_FILE = 2'h1;
|
|
// MX_DST
|
|
parameter [1:0]
|
|
MXDST_NULL = 2'h0,
|
|
MXDST_EXT = 2'h1,
|
|
MXDST_WREG = 2'h2,
|
|
MXDST_FILE = 2'h3;
|
|
|
|
// MX_ALU
|
|
parameter [3:0]
|
|
MXALU_XOR = 4'h0,
|
|
MXALU_IOR = 4'h1,
|
|
MXALU_AND = 4'h2,
|
|
MXALU_SWAP = 4'h3,
|
|
MXALU_ADD = 4'h4,
|
|
MXALU_ADDC = 4'h5,
|
|
MXALU_SUB = 4'h6,
|
|
MXALU_SUBC = 4'h7,
|
|
MXALU_RLNC = 4'h8,
|
|
MXALU_RLC = 4'h9,
|
|
MXALU_RRNC = 4'hA,
|
|
MXALU_RRC = 4'hB,
|
|
MXALU_NEG = 4'hC,
|
|
// EXTRA
|
|
MXALU_MOVLB = 4'hC,
|
|
MXALU_DAW = 4'hD,
|
|
MXALU_LFSR = 4'hE,
|
|
MXALU_MUL = 4'hF;
|
|
|
|
// MX_BSR
|
|
parameter [1:0]
|
|
MXBSR_BSR = 2'o3,
|
|
MXBSR_BSA = 2'o2,
|
|
MXBSR_LIT = 2'o1,
|
|
MXBSR_NUL = 2'o0;
|
|
|
|
// MX_SKP
|
|
parameter [2:0]
|
|
MXSKP_SZ = 3'o1,
|
|
MXSKP_SNZ = 3'o2,
|
|
MXSKP_SNC = 3'o3,
|
|
MXSKP_SU = 3'o4,
|
|
MXSKP_SCC = 3'o7,
|
|
MXSKP_NON = 3'o0;
|
|
|
|
// NPC_MX
|
|
parameter [2:0]
|
|
MXNPC_FAR = 3'o3,
|
|
MXNPC_NEAR = 3'o2,
|
|
MXNPC_BCC = 3'o7,
|
|
MXNPC_RET = 3'o1,
|
|
MXNPC_RESET = 3'o4,
|
|
MXNPC_ISRH = 3'o5,
|
|
MXNPC_ISRL = 3'o6,
|
|
MXNPC_INC = 3'o0;
|
|
|
|
// MX_STA
|
|
parameter [2:0]
|
|
MXSTA_ALL = 3'o7,
|
|
MXSTA_CZN = 3'o1,
|
|
MXSTA_ZN = 3'o2,
|
|
MXSTA_Z = 3'o3,
|
|
MXSTA_C = 3'o4,
|
|
MXSTA_NONE = 3'o0;
|
|
|
|
// BCC_MX
|
|
parameter [2:0]
|
|
MXBCC_BZ = 3'o0,
|
|
MXBCC_BNZ = 3'o1,
|
|
MXBCC_BC = 3'o2,
|
|
MXBCC_BNC = 3'o3,
|
|
MXBCC_BOV = 3'o4,
|
|
MXBCC_BNOV = 3'o5,
|
|
MXBCC_BN = 3'o6,
|
|
MXBCC_BNN = 3'o7;
|
|
|
|
// STK_MX
|
|
parameter [1:0]
|
|
MXSTK_PUSH = 2'o2,
|
|
MXSTK_POP = 2'o1,
|
|
MXSTK_NONE = 2'o0;
|
|
|
|
// SHADOW MX
|
|
parameter [1:0]
|
|
MXSHA_CALL = 2'o2,
|
|
MXSHA_RET = 2'o1,
|
|
MXSHA_NONE = 2'o0;
|
|
|
|
// TBLRD/TBLWT MX
|
|
parameter [3:0]
|
|
MXTBL_RD = 4'h8,
|
|
MXTBL_RDINC = 4'h9,
|
|
MXTBL_RDDEC = 4'hA,
|
|
MXTBL_RDPRE = 4'hB,
|
|
MXTBL_WT = 4'hC,
|
|
MXTBL_WTINC = 4'hD,
|
|
MXTBL_WTDEC = 4'hE,
|
|
MXTBL_WTPRE = 4'hF,
|
|
MXTBL_NOP = 4'h0;
|
|
|
// Machine Status
|
// Machine Status
|
//output [3:0] qena_o;
|
//output [3:0] qena_o;
|
//output [1:0] qfsm_o;
|
//output [1:0] qfsm_o;
|
//output [1:0] qmod_o;
|
//output [1:0] qmod_o;
|
|
|
| Line 118... |
Line 248... |
* Clock and reset generation using on chip DCM/PLL.
|
* Clock and reset generation using on chip DCM/PLL.
|
*/
|
*/
|
|
|
wire clk = clk_i;
|
wire clk = clk_i;
|
wire xrst = rst_i;
|
wire xrst = rst_i;
|
|
wire qrst = rRESET;
|
assign wb_clk_o = clk_i;
|
assign wb_clk_o = clk_i;
|
assign wb_rst_o = ~rRESET;
|
assign wb_rst_o = ~rRESET;
|
|
|
// WDT
|
// WDT
|
reg [WSIZ:0] rWDT;
|
reg [WSIZ:0] rWDT;
|
| Line 153... |
Line 284... |
/*
|
/*
|
* DESCRIPTION
|
* DESCRIPTION
|
* AE18 MCU conductor.
|
* AE18 MCU conductor.
|
* Determines and generates the control signal for machine states.
|
* Determines and generates the control signal for machine states.
|
*/
|
*/
|
// State Registers
|
|
parameter [2:0]
|
|
FSM_RUN = 4'h0,
|
|
FSM_ISRL = 4'h1,
|
|
FSM_ISRH = 4'h2,
|
|
FSM_SLEEP = 4'h3;
|
|
|
|
parameter [1:0]
|
|
FSM_Q0 = 2'h0,
|
|
FSM_Q1 = 2'h1,
|
|
FSM_Q2 = 2'h2,
|
|
FSM_Q3 = 2'h3;
|
|
|
|
reg [3:0] rQCLK;
|
reg [3:0] rQCLK;
|
reg [1:0] rQCNT;
|
reg [1:0] rQCNT;
|
reg [1:0] rFSM, rNXT;
|
reg [1:0] rFSM, rNXT;
|
|
|
//assign qena_o = rQCLK;
|
//assign qena_o = rQCLK;
|
//assign qfsm_o = rQCNT;
|
//assign qfsm_o = rQCNT;
|
//assign qmod_o = rFSM;
|
//assign qmod_o = rFSM;
|
|
|
wire qrst = rRESET;
|
|
wire xrun = !((iwb_stb_o ^ iwb_ack_i) | (dwb_stb_o ^ dwb_ack_i));
|
wire xrun = !((iwb_stb_o ^ iwb_ack_i) | (dwb_stb_o ^ dwb_ack_i));
|
wire qrun = (rFSM != FSM_SLEEP);
|
wire qrun = (rFSM != FSM_SLEEP);
|
wire [3:0] qena = rQCLK;
|
wire [3:0] qena = rQCLK;
|
wire [1:0] qfsm = rQCNT;
|
wire [1:0] qfsm = rQCNT;
|
|
|
| Line 303... |
Line 421... |
rIWBADR <= #1 (rMXTBL == MXTBL_NOP) ? rIWBADR : {rTBLPTRU,rTBLPTRH,rTBLPTRL[7:1]};
|
rIWBADR <= #1 (rMXTBL == MXTBL_NOP) ? rIWBADR : {rTBLPTRU,rTBLPTRH,rTBLPTRL[7:1]};
|
end
|
end
|
endcase // case(qfsm)
|
endcase // case(qfsm)
|
|
|
// PC next calculation
|
// PC next calculation
|
|
wire [ISIZ-2:0] wPCINC = rIWBADR + 1;
|
wire [ISIZ-2:0] wPCBCC = (!rNSKP) ? wPCINC :
|
wire [ISIZ-2:0] wPCBCC = (!rNSKP) ? wPCINC :
|
(rBCC) ? rIWBADR + {{(ISIZ-8){rIREG[7]}},rIREG[7:0]} : wPCINC;
|
(rBCC) ? rIWBADR + {{(ISIZ-8){rIREG[7]}},rIREG[7:0]} : wPCINC;
|
wire [ISIZ-2:0] wPCNEAR = (!rNSKP) ? wPCINC : rIWBADR + {{(ISIZ-11){rIREG[10]}},rIREG[10:0]};
|
wire [ISIZ-2:0] wPCNEAR = (!rNSKP) ? wPCINC : rIWBADR + {{(ISIZ-11){rIREG[10]}},rIREG[10:0]};
|
wire [ISIZ-2:0] wPCFAR = (!rNSKP) ? wPCINC : {rROMLAT[11:0],rIREG[7:0]};
|
wire [ISIZ-2:0] wPCFAR = (!rNSKP) ? wPCINC : {rROMLAT[11:0],rIREG[7:0]};
|
wire [ISIZ-2:0] wPCINC = rIWBADR + 1;
|
|
wire [ISIZ-2:0] wPCSTK = (!rNSKP) ? wPCINC : {rTOSU, rTOSH, rTOSL[7:1]};
|
wire [ISIZ-2:0] wPCSTK = (!rNSKP) ? wPCINC : {rTOSU, rTOSH, rTOSL[7:1]};
|
|
|
always @(negedge clk or negedge qrst)
|
always @(negedge clk or negedge qrst)
|
if (!qrst) begin
|
if (!qrst) begin
|
/*AUTORESET*/
|
/*AUTORESET*/
|
| Line 535... |
Line 653... |
|
|
// MX INT
|
// MX INT
|
wire fINT = ^rINTF;
|
wire fINT = ^rINTF;
|
|
|
// MX_SRC
|
// MX_SRC
|
parameter [1:0]
|
|
MXSRC_MASK = 2'h2,
|
|
MXSRC_LIT = 2'h3,
|
|
MXSRC_WREG = 2'h0,
|
|
MXSRC_FILE = 2'h1;
|
|
wire [1:0] wMXSRC =
|
wire [1:0] wMXSRC =
|
(fMOVLW|fRETLW|fCOMF|
|
(fMOVLW|fRETLW|fCOMF|
|
fDECF|fDECFSZ|fDCFSNZ|
|
fDECF|fDECFSZ|fDCFSNZ|
|
fINCF|fINCFSZ|fINFSNZ|
|
fINCF|fINCFSZ|fINFSNZ|
|
fMOVF|fMOVFF|fMOVWF|
|
fMOVF|fMOVFF|fMOVWF|
|
| Line 551... |
Line 664... |
(fBSF|fBTG|fBTFSC|fBTFSS) ? MXSRC_MASK :
|
(fBSF|fBTG|fBTFSC|fBTFSS) ? MXSRC_MASK :
|
(fBCF|fCPFSLT|fSUBFWB) ? MXSRC_FILE :
|
(fBCF|fCPFSLT|fSUBFWB) ? MXSRC_FILE :
|
MXSRC_WREG;
|
MXSRC_WREG;
|
|
|
// MX_TGT
|
// MX_TGT
|
parameter [1:0]
|
|
MXTGT_MASK = 2'h2,
|
|
MXTGT_LIT = 2'h3,
|
|
MXTGT_WREG = 2'h0,
|
|
MXTGT_FILE = 2'h1;
|
|
wire [1:0] wMXTGT =
|
wire [1:0] wMXTGT =
|
(fBCF) ? MXTGT_MASK :
|
(fBCF) ? MXTGT_MASK :
|
(fRETLW|fMOVLW|
|
(fRETLW|fMOVLW|
|
fMULLW|
|
fMULLW|
|
fADDLW|fSUBLW|
|
fADDLW|fSUBLW|
|
| Line 575... |
Line 683... |
fRLCF|fRLNCF|fRRCF|fRRNCF|
|
fRLCF|fRLNCF|fRRCF|fRRNCF|
|
fTSTFSZ) ? MXTGT_FILE :
|
fTSTFSZ) ? MXTGT_FILE :
|
MXTGT_WREG;
|
MXTGT_WREG;
|
|
|
// MX_DST
|
// MX_DST
|
parameter [1:0]
|
|
MXDST_NULL = 2'h0,
|
|
MXDST_EXT = 2'h1,
|
|
MXDST_WREG = 2'h2,
|
|
MXDST_FILE = 2'h3;
|
|
wire [1:0] wMXDST =
|
wire [1:0] wMXDST =
|
(fMULWF|fMULLW|fMOVLB|fLFSR|fDAW) ? MXDST_EXT :
|
(fMULWF|fMULLW|fMOVLB|fLFSR|fDAW) ? MXDST_EXT :
|
(fBCF|fBSF|fBTG|
|
(fBCF|fBSF|fBTG|
|
fCLRF|
|
fCLRF|
|
fMOVFF|fMOVWF|
|
fMOVFF|fMOVWF|
|
| Line 599... |
Line 702... |
fINCF|fINCFSZ|fINFSNZ|
|
fINCF|fINCFSZ|fINFSNZ|
|
fRLCF|fRLNCF|fRRCF|fRRNCF) ? {1'b1,fOPCL[1]} :
|
fRLCF|fRLNCF|fRRCF|fRRNCF) ? {1'b1,fOPCL[1]} :
|
MXDST_NULL;
|
MXDST_NULL;
|
|
|
// MX_ALU
|
// MX_ALU
|
parameter [3:0]
|
|
MXALU_XOR = 4'h0,
|
|
MXALU_IOR = 4'h1,
|
|
MXALU_AND = 4'h2,
|
|
MXALU_SWAP = 4'h3,
|
|
MXALU_ADD = 4'h4,
|
|
MXALU_ADDC = 4'h5,
|
|
MXALU_SUB = 4'h6,
|
|
MXALU_SUBC = 4'h7,
|
|
MXALU_RLNC = 4'h8,
|
|
MXALU_RLC = 4'h9,
|
|
MXALU_RRNC = 4'hA,
|
|
MXALU_RRC = 4'hB,
|
|
MXALU_NEG = 4'hC,
|
|
// EXTRA
|
|
MXALU_MOVLB = 4'hC,
|
|
MXALU_DAW = 4'hD,
|
|
MXALU_LFSR = 4'hE,
|
|
MXALU_MUL = 4'hF;
|
|
wire [3:0] wMXALU =
|
wire [3:0] wMXALU =
|
(fDAW) ? MXALU_DAW :
|
(fDAW) ? MXALU_DAW :
|
(fMOVLB) ? MXALU_MOVLB :
|
(fMOVLB) ? MXALU_MOVLB :
|
(fLFSR) ? MXALU_LFSR :
|
(fLFSR) ? MXALU_LFSR :
|
(fMULLW|fMULWF) ? MXALU_MUL :
|
(fMULLW|fMULWF) ? MXALU_MUL :
|
| Line 643... |
Line 727... |
fRETLW|fBTFSS|fBTFSC|fTSTFSZ|
|
fRETLW|fBTFSS|fBTFSC|fTSTFSZ|
|
fMOVF|fMOVFF|fMOVWF|fMOVLW) ? MXALU_AND :
|
fMOVF|fMOVFF|fMOVWF|fMOVLW) ? MXALU_AND :
|
MXALU_XOR;
|
MXALU_XOR;
|
|
|
// MX_BSR
|
// MX_BSR
|
parameter [1:0]
|
|
MXBSR_BSR = 2'o3,
|
|
MXBSR_BSA = 2'o2,
|
|
MXBSR_LIT = 2'o1,
|
|
MXBSR_NUL = 2'o0;
|
|
wire [1:0] wMXBSR =
|
wire [1:0] wMXBSR =
|
(fMOVFF) ? MXBSR_LIT :
|
(fMOVFF) ? MXBSR_LIT :
|
(fBCF|fBSF|fBTG|fBTFSS|fBTFSC|
|
(fBCF|fBSF|fBTG|fBTFSS|fBTFSC|
|
fANDWF|fIORWF|fXORWF|fCOMF|
|
fANDWF|fIORWF|fXORWF|fCOMF|
|
fADDWF|fADDWFC|fSUBWF|fSUBWFB|fSUBFWB|fMULWF|
|
fADDWF|fADDWFC|fSUBWF|fSUBWFB|fSUBFWB|fMULWF|
|
| Line 660... |
Line 739... |
fINCF|fINCFSZ|fINFSNZ|fDECF|fDECFSZ|fDCFSNZ|
|
fINCF|fINCFSZ|fINFSNZ|fDECF|fDECFSZ|fDCFSNZ|
|
fRLCF|fRLNCF|fRRCF|fRRNCF) ? {1'b1, fOPCL[0]} :
|
fRLCF|fRLNCF|fRRCF|fRRNCF) ? {1'b1, fOPCL[0]} :
|
MXBSR_NUL;
|
MXBSR_NUL;
|
|
|
// MX_SKP
|
// MX_SKP
|
parameter [2:0]
|
|
MXSKP_SZ = 3'o1,
|
|
MXSKP_SNZ = 3'o2,
|
|
MXSKP_SNC = 3'o3,
|
|
MXSKP_SU = 3'o4,
|
|
MXSKP_SCC = 3'o7,
|
|
MXSKP_NON = 3'o0;
|
|
wire [2:0] wMXSKP =
|
wire [2:0] wMXSKP =
|
(fTSTFSZ|fINCFSZ|fDECFSZ|fCPFSEQ|fBTFSC) ? MXSKP_SZ :
|
(fTSTFSZ|fINCFSZ|fDECFSZ|fCPFSEQ|fBTFSC) ? MXSKP_SZ :
|
(fINFSNZ|fDCFSNZ|fBTFSS) ? MXSKP_SNZ :
|
(fINFSNZ|fDCFSNZ|fBTFSS) ? MXSKP_SNZ :
|
(fCPFSGT|fCPFSLT) ? MXSKP_SNC :
|
(fCPFSGT|fCPFSLT) ? MXSKP_SNC :
|
(fBC|fBNC|fBZ|fBNZ|fBN|fBNN|fBOV|fBNOV) ? MXSKP_SCC :
|
(fBC|fBNC|fBZ|fBNZ|fBN|fBNN|fBOV|fBNOV) ? MXSKP_SCC :
|
(fBRA|fCALL|fRCALL|fGOTO|fRETFIE|fRETURN|fRETLW) ? MXSKP_SU :
|
(fBRA|fCALL|fRCALL|fGOTO|fRETFIE|fRETURN|fRETLW) ? MXSKP_SU :
|
MXSKP_NON;
|
MXSKP_NON;
|
|
|
// NPC_MX
|
// NPC_MX
|
parameter [2:0]
|
|
MXNPC_FAR = 3'o3,
|
|
MXNPC_NEAR = 3'o2,
|
|
MXNPC_BCC = 3'o7,
|
|
MXNPC_RET = 3'o1,
|
|
MXNPC_RESET = 3'o4,
|
|
MXNPC_ISRH = 3'o5,
|
|
MXNPC_ISRL = 3'o6,
|
|
MXNPC_INC = 3'o0;
|
|
wire [2:0] wMXNPC =
|
wire [2:0] wMXNPC =
|
(fBC|fBNC|fBN|fBNN|fBOV|fBNOV|fBZ|fBNZ) ? MXNPC_BCC :
|
(fBC|fBNC|fBN|fBNN|fBOV|fBNOV|fBZ|fBNZ) ? MXNPC_BCC :
|
(fBRA|fRCALL) ? MXNPC_NEAR :
|
(fBRA|fRCALL) ? MXNPC_NEAR :
|
(fCALL|fGOTO) ? MXNPC_FAR :
|
(fCALL|fGOTO) ? MXNPC_FAR :
|
(fRETFIE|fRETURN|fRETLW) ? MXNPC_RET :
|
(fRETFIE|fRETURN|fRETLW) ? MXNPC_RET :
|
MXNPC_INC;
|
MXNPC_INC;
|
|
|
// MX_STA
|
// MX_STA
|
parameter [2:0]
|
|
MXSTA_ALL = 3'o7,
|
|
MXSTA_CZN = 3'o1,
|
|
MXSTA_ZN = 3'o2,
|
|
MXSTA_Z = 3'o3,
|
|
MXSTA_C = 3'o4,
|
|
MXSTA_NONE = 3'o0;
|
|
wire [2:0] wMXSTA =
|
wire [2:0] wMXSTA =
|
(fADDLW|fADDWF|fADDWFC|
|
(fADDLW|fADDWF|fADDWFC|
|
fSUBLW|fSUBWF|fSUBWFB|fSUBFWB|
|
fSUBLW|fSUBWF|fSUBWFB|fSUBFWB|
|
fDECF|fINCF|fNEGF) ? MXSTA_ALL :
|
fDECF|fINCF|fNEGF) ? MXSTA_ALL :
|
(fRRCF|fRLCF) ? MXSTA_CZN :
|
(fRRCF|fRLCF) ? MXSTA_CZN :
|
| Line 713... |
Line 769... |
(fDAW) ? MXSTA_C :
|
(fDAW) ? MXSTA_C :
|
(fCLRF) ? MXSTA_Z :
|
(fCLRF) ? MXSTA_Z :
|
MXSTA_NONE;
|
MXSTA_NONE;
|
|
|
// BCC_MX
|
// BCC_MX
|
parameter [2:0]
|
|
MXBCC_BZ = 3'o0,
|
|
MXBCC_BNZ = 3'o1,
|
|
MXBCC_BC = 3'o2,
|
|
MXBCC_BNC = 3'o3,
|
|
MXBCC_BOV = 3'o4,
|
|
MXBCC_BNOV = 3'o5,
|
|
MXBCC_BN = 3'o6,
|
|
MXBCC_BNN = 3'o7;
|
|
wire [2:0] wMXBCC = fOPCL[2:0];
|
wire [2:0] wMXBCC = fOPCL[2:0];
|
|
|
// STK_MX
|
// STK_MX
|
parameter [1:0]
|
|
MXSTK_PUSH = 2'o2,
|
|
MXSTK_POP = 2'o1,
|
|
MXSTK_NONE = 2'o0;
|
|
wire [1:0] wMXSTK =
|
wire [1:0] wMXSTK =
|
(fRETFIE|fRETLW|fRETURN|fPOP) ? MXSTK_POP :
|
(fRETFIE|fRETLW|fRETURN|fPOP) ? MXSTK_POP :
|
(fCALL|fRCALL|fPUSH|fINT) ? MXSTK_PUSH :
|
(fCALL|fRCALL|fPUSH|fINT) ? MXSTK_PUSH :
|
MXSTK_NONE;
|
MXSTK_NONE;
|
|
|
// SHADOW MX
|
// SHADOW MX
|
parameter [1:0]
|
|
MXSHA_CALL = 2'o2,
|
|
MXSHA_RET = 2'o1,
|
|
MXSHA_NONE = 2'o0;
|
|
|
|
wire [1:0] wMXSHA =
|
wire [1:0] wMXSHA =
|
(fCALL) ? {fOPCL[0] ,1'b0} :
|
(fCALL) ? {fOPCL[0] ,1'b0} :
|
(fINT) ? {MXSHA_CALL} :
|
(fINT) ? {MXSHA_CALL} :
|
(fRETURN|fRETFIE) ? {1'b0,fOPCK[0]} :
|
(fRETURN|fRETFIE) ? {1'b0,fOPCK[0]} :
|
1'b0;
|
1'b0;
|
|
|
// TBLRD/TBLWT MX
|
// TBLRD/TBLWT MX
|
parameter [3:0]
|
|
MXTBL_RD = 4'h8,
|
|
MXTBL_RDINC = 4'h9,
|
|
MXTBL_RDDEC = 4'hA,
|
|
MXTBL_RDPRE = 4'hB,
|
|
MXTBL_WT = 4'hC,
|
|
MXTBL_WTINC = 4'hD,
|
|
MXTBL_WTDEC = 4'hE,
|
|
MXTBL_WTPRE = 4'hF,
|
|
MXTBL_NOP = 4'h0;
|
|
wire [3:0] wMXTBL =
|
wire [3:0] wMXTBL =
|
(fTBLRDWT) ? fOPCK[3:0] :
|
(fTBLRDWT) ? fOPCK[3:0] :
|
MXTBL_NOP;
|
MXTBL_NOP;
|
|
|
// FSR DECODER
|
// FSR DECODER
|
| Line 1164... |
Line 1192... |
FSM_Q2: rDWBSTB <= #1 (rMXDST == MXDST_FILE);
|
FSM_Q2: rDWBSTB <= #1 (rMXDST == MXDST_FILE);
|
FSM_Q0: rDWBSTB <= #1 ((rMXSRC == MXSRC_FILE) | (rMXTGT == MXTGT_FILE));
|
FSM_Q0: rDWBSTB <= #1 ((rMXSRC == MXSRC_FILE) | (rMXTGT == MXTGT_FILE));
|
default: rDWBSTB <= #1 1'b0;
|
default: rDWBSTB <= #1 1'b0;
|
endcase // case(qfsm)
|
endcase // case(qfsm)
|
|
|
|
// STACK
|
|
wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
|
|
wire [ISIZ-1:0] wSTKR;
|
|
wire wSTKE = (qena[1]);
|
|
|
|
ae18_aram #(ISIZ,5)
|
|
stack (
|
|
.wdat(wSTKW), .rdat(wSTKR),
|
|
.radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
|
|
.we(wSTKE),
|
|
// Inputs
|
|
.clk (clk));
|
|
|
/*
|
/*
|
* SFR Bank
|
* SFR Bank
|
*/
|
*/
|
parameter [15:0]
|
parameter [15:0]
|
//aRCON = 16'hFFD0,
|
//aRCON = 16'hFFD0,
|
| Line 1579... |
Line 1620... |
if (!qrst)
|
if (!qrst)
|
rNSKP <= 1'h1;
|
rNSKP <= 1'h1;
|
else if (qena[3])
|
else if (qena[3])
|
rNSKP <= #1 ((rDWBADR == aPCL) & rDWBWE) ? 1'b0 : ~(wSKP & rNSKP);
|
rNSKP <= #1 ((rDWBADR == aPCL) & rDWBWE) ? 1'b0 : ~(wSKP & rNSKP);
|
|
|
// STACK
|
|
wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
|
|
wire [ISIZ-1:0] wSTKR;
|
|
wire wSTKE = (qena[1]);
|
|
|
|
ae18_aram #(ISIZ,5)
|
|
stack (
|
|
.wdat(wSTKW), .rdat(wSTKR),
|
|
.radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
|
|
.we(wSTKE),
|
|
// Inputs
|
|
.clk (clk));
|
|
|
|
endmodule // ae18_core
|
endmodule // ae18_core
|
|
|
No newline at end of file
|
No newline at end of file
|
