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// -*- Mode: Verilog -*-
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// Filename : ae18_core.v
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// Description : PIC18 compatible core.
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// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Created On : Fri Dec 22 16:09:33 2006
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// Last Modified By: $Author: sybreon $
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// Last Modified On: $Date: 2007-04-03 22:13:25 $
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// Update Count : $Revision: 1.6 $
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// Status : $State: Exp $
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/*
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/*
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* $Id: ae18_core.v,v 1.6 2007-04-03 22:13:25 sybreon Exp $
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* $Id: ae18_core.v,v 1.7 2007-04-13 22:18:51 sybreon Exp $
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*
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*
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* AE18 8-bit Microprocessor Core
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* AE18 8-bit Microprocessor Core
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published by
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* under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 2.1 of the License,
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* the Free Software Foundation; either version 2.1 of the License,
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* or (at your option) any later version.
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* or (at your option) any later version.
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*
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*
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* This library is distributed in the hope that it will be useful, but
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* License for more details.
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* Lesser General Public License for more details.
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*
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*
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* You should have received a copy of the GNU Lesser General Public License
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* You should have received a copy of the GNU Lesser General Public
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* along with this library; if not, write to the Free Software Foundation, Inc.,
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* License along with this library; if not, write to the Free Software
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*
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*
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* DESCRIPTION
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* DESCRIPTION
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* This core provides a PIC18 software compatible core. It does not provide
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* This core provides a PIC18 software compatible core. It does not provide
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* any of the additional functionality needed to form a full PIC18 micro-
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* any of the additional functionality needed to form a full PIC18 micro-
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* controller system. Additional functionality such as I/O devices would
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* controller system. Additional functionality such as I/O devices would
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* need to be integrated with the core. This core provides the necessary
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* need to be integrated with the core. This core provides the necessary
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* signals to wire up WISHBONE compatible devices to it.
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* signals to wire up WISHBONE compatible devices to it.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.6 2007/04/03 22:13:25 sybreon
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* Fixed various bugs:
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* - STATUS,C not correct for subtraction instructions
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* - Data memory indirect addressing mode bugs
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* - Other minor fixes
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*
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* Revision 1.5 2007/03/04 23:26:37 sybreon
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* Revision 1.5 2007/03/04 23:26:37 sybreon
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* Rearranged code to make it synthesisable.
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* Rearranged code to make it synthesisable.
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*
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*
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* Revision 1.4 2006/12/29 18:08:56 sybreon
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* Revision 1.4 2006/12/29 18:08:56 sybreon
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* Minor code clean up
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* Minor code clean up
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// STACK
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// STACK
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wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
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wire [ISIZ-1:0] wSTKW = {rTOSU,rTOSH,rTOSL};
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wire [ISIZ-1:0] wSTKR;
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wire [ISIZ-1:0] wSTKR;
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wire wSTKE = (qena[1]);
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wire wSTKE = (qena[1]);
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ae18_aram #(ISIZ,5)
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reg [ISIZ-1:0] rSTKRAM [0:31];
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stack (
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.wdat(wSTKW), .rdat(wSTKR),
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assign wSTKR = rSTKRAM[rSTKPTR[4:0]];
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.radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
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always @(posedge clk)
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.we(wSTKE),
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if (wSTKE)
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// Inputs
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rSTKRAM[rSTKPTR_[4:0]] <= wSTKW;
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.clk (clk));
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/*
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/*
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* SFR Bank
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* SFR Bank
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*/
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*/
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parameter [15:0]
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parameter [15:0]
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