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// $Id: aeMB_bpcu.v,v 1.1 2007-11-02 03:25:39 sybreon Exp $
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// $Id: aeMB_bpcu.v,v 1.2 2007-11-02 19:20:58 sybreon Exp $
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//
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//
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// AEMB BRANCH PROGRAMME COUNTER UNIT
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// AEMB BRANCH PROGRAMME COUNTER UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2007/11/02 03:25:39 sybreon
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// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
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// Fixed various minor data hazard bugs.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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module aeMB_bpcu (/*AUTOARG*/
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module aeMB_bpcu (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_adr_o, rPC, rPCLNK, rBRA, rDLY,
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iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, rATOM,
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// Inputs
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// Inputs
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rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, rXCE, gclk, grst,
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rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, rXCE, gclk, grst,
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gena
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gena
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);
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);
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parameter IW = 24;
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parameter IW = 24;
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// INTERNAL
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// INTERNAL
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output [31:2] rPC, rPCLNK;
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output [31:2] rPC, rPCLNK;
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output rBRA;
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output rBRA;
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output rDLY;
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output rDLY;
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output [1:0] rATOM;
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input [1:0] rMXALT;
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input [1:0] rMXALT;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD, rRA;
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input [4:0] rRD, rRA;
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input [31:0] rRESULT; // ALU
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input [31:0] rRESULT; // ALU
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input [31:0] rDWBDI; // RAM
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input [31:0] rDWBDI; // RAM
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input [1:0] rXCE;
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input [1:0] rXCE;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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// BRANCH
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// --- BRANCH CONTROL --------------------------------------------
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// Controls the branch and delay flags
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wire fRTD = (rOPC == 6'o55);
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wire fRTD = (rOPC == 6'o55);
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wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
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wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
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wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
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wire [31:0] wREGA;
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wire [31:0] wREGA;
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3'o4: xXCC <= wBGT;
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3'o4: xXCC <= wBGT;
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3'o5: xXCC <= wBGE;
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3'o5: xXCC <= wBGE;
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default: xXCC <= 1'bX;
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default: xXCC <= 1'bX;
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endcase // case (rRD[2:0])
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endcase // case (rRD[2:0])
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// DELAY SLOT
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reg rBRA, xBRA;
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reg rBRA, xBRA;
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reg rDLY, xDLY;
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reg rDLY, xDLY;
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wire fSKIP = rBRA & !rDLY;
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wire fSKIP = rBRA & !rDLY;
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always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD
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always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD
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or xXCC)
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or rXCE or xXCC)
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if (rBRA) begin
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if (rBRA | |rXCE) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xBRA <= 1'h0;
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xBRA <= 1'h0;
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xDLY <= 1'h0;
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xDLY <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD;
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xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD;
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xBRA <= (fRTD | fBRU) ? 1'b1 :
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xBRA <= (fRTD | fBRU) ? 1'b1 :
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(fBCC) ? xXCC :
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(fBCC) ? xXCC :
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1'b0;
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1'b0;
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/*
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case (rXCE)
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2'o1: xBRA <= 1'b0;
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default: xBRA <= (fRTD | fBRU) ? 1'b1 :
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(fBCC) ? xXCC :
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1'b0;
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endcase // case (rXCE)
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*/
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end
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end
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reg [31:2] rPCLNK, xPCLNK;
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// --- PC PIPELINE ------------------------------------------------
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always @(/*AUTOSENSE*/fSKIP or rBRA or rPC or rRESULT)
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// PC and related changes
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if (fSKIP) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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xPCLNK <= 30'h0;
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// End of automatics
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end else begin
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xPCLNK <= (rBRA) ? rRESULT[31:2] : rPC;
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end
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// PC Changes - (NXT, BRA, INT)
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reg [31:2] rIPC, xIPC;
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reg [31:2] rIPC, xIPC;
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reg [31:2] rPC, xPC;
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reg [31:2] rPC, xPC;
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reg [31:2] rPCLNK, xPCLNK;
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assign iwb_adr_o = rIPC[IW-1:2];
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assign iwb_adr_o = rIPC[IW-1:2];
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always @(/*AUTOSENSE*/rBRA or rIPC or rRESULT) begin
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xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
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always @(/*AUTOSENSE*/rATOM or rBRA or rIPC or rPC or rRESULT
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/*
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or rXCE) begin
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case (rXCE)
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xPCLNK <= (^rATOM) ? rPC : rPC;
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2'o1: xIPC <= 32'h04;
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//xPCLNK <= rPC;
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default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
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//xPC <= (^rATOM) ? rIPC : rRESULT[31:2];
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endcase // case (rXCE)
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*/
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xPC <= rIPC;
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xPC <= rIPC;
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//xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
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case (rXCE)
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2'o1: xIPC <= 30'h2;
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2'o2: xIPC <= 30'h4;
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2'o3: xIPC <= 30'h6;
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default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
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endcase // case (rXCE)
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end
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end
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// --- ATOMIC CONTROL ---------------------------------------------
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// This is used to indicate 'safe' instruction borders.
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wire wIMM = (rOPC == 6'o54) & !fSKIP;
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wire wRTD = (rOPC == 6'o55) & !fSKIP;
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wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP;
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wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP;
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wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA);
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reg [1:0] rATOM, xATOM;
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always @(/*AUTOSENSE*/fATOM or rATOM)
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xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)};
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// --- SYNC PIPELINE ----------------------------------------------
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// SYNC
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rATOM <= 2'h0;
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rBRA <= 1'h0;
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rBRA <= 1'h0;
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rDLY <= 1'h0;
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rDLY <= 1'h0;
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rIPC <= 30'h0;
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rIPC <= 30'h0;
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rPC <= 30'h0;
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rPC <= 30'h0;
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rPCLNK <= 30'h0;
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rPCLNK <= 30'h0;
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rIPC <= #1 xIPC;
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rIPC <= #1 xIPC;
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rBRA <= #1 xBRA;
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rBRA <= #1 xBRA;
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rPC <= #1 xPC;
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rPC <= #1 xPC;
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rPCLNK <= #1 xPCLNK;
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rPCLNK <= #1 xPCLNK;
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rDLY <= #1 xDLY;
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rDLY <= #1 xDLY;
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rATOM <= #1 xATOM;
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end
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end
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// synopsys translate_off
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// synopsys translate_on
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endmodule // aeMB_bpcu
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endmodule // aeMB_bpcu
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