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/*
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/*
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* $Id: aeMB_core.v,v 1.4 2007-04-25 22:15:04 sybreon Exp $
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* $Id: aeMB_core.v,v 1.5 2007-04-27 00:23:55 sybreon Exp $
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*
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*
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* AEMB 32-bit Microblaze Compatible Core
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* AEMB 32-bit Microblaze Compatible Core
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* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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*
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*
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* This library is free software; you can redistribute it and/or modify it
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* This library is free software; you can redistribute it and/or
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* under the terms of the GNU Lesser General Public License as published by
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* modify it under the terms of the GNU Lesser General Public License
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* the Free Software Foundation; either version 2.1 of the License,
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* as published by the Free Software Foundation; either version 2.1 of
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* or (at your option) any later version.
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* the License, or (at your option) any later version.
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*
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*
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* This library is distributed in the hope that it will be useful, but
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* License for more details.
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* Lesser General Public License for more details.
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*
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*
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* You should have received a copy of the GNU Lesser General Public License
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* You should have received a copy of the GNU Lesser General Public
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* along with this library; if not, write to the Free Software Foundation, Inc.,
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* License along with this library; if not, write to the Free Software
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*
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*
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* DESCRIPTION
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* DESCRIPTION
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* Microblaze compatible, WISHBONE compliant hardware core. This core is
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* Microblaze compatible, WISHBONE compliant hardware core. This core is
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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* capable of executing software compile for EDK 2.1 using GCC. It has the
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* capability of handling interrupts as well as exceptions.
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* capability of handling interrupts as well as exceptions.
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*
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*
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* HISTORY
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* HISTORY
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* $Log: not supported by cvs2svn $
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* $Log: not supported by cvs2svn $
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* Revision 1.4 2007/04/25 22:15:04 sybreon
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* Added support for 8-bit and 16-bit data types.
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*
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Revision 1.3 2007/04/11 04:30:43 sybreon
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* Added pipeline stalling from incomplete bus cycles.
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* Added pipeline stalling from incomplete bus cycles.
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* Separated sync and async portions of code.
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* Separated sync and async portions of code.
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*
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*
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* Revision 1.2 2007/04/04 06:13:23 sybreon
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* Revision 1.2 2007/04/04 06:13:23 sybreon
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Line 60... |
output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v
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output [3:0] dwb_sel_o; // From aslu of aeMB_aslu.v
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output [3:0] dwb_sel_o; // From aslu of aeMB_aslu.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_stb_o; // From decode of aeMB_decode.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output dwb_we_o; // From decode of aeMB_decode.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
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output iwb_stb_o; // From decode of aeMB_decode.v
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output iwb_stb_o; // From fetch of aeMB_fetch.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To control of aeMB_control.v
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input dwb_ack_i; // To control of aeMB_control.v
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v
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input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v
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Line 87... |
wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
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wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v
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wire rDWBSTB; // From decode of aeMB_decode.v
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wire rDWBSTB; // From decode of aeMB_decode.v
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wire rDWBWE; // From decode of aeMB_decode.v
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wire rDWBWE; // From decode of aeMB_decode.v
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wire [1:0] rFSM; // From control of aeMB_control.v
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wire [1:0] rFSM; // From control of aeMB_control.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire [15:0] rIMM; // From decode of aeMB_decode.v
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wire rIWBSTB; // From decode of aeMB_decode.v
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wire rIWBSTB; // From fetch of aeMB_fetch.v
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wire rLNK; // From decode of aeMB_decode.v
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wire rLNK; // From decode of aeMB_decode.v
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wire [1:0] rMXALU; // From decode of aeMB_decode.v
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wire [1:0] rMXALU; // From decode of aeMB_decode.v
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wire [1:0] rMXLDST; // From decode of aeMB_decode.v
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wire [1:0] rMXLDST; // From decode of aeMB_decode.v
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wire [1:0] rMXSRC; // From decode of aeMB_decode.v
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wire [1:0] rMXSRC; // From decode of aeMB_decode.v
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wire [1:0] rMXTGT; // From decode of aeMB_decode.v
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wire [1:0] rMXTGT; // From decode of aeMB_decode.v
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wire [5:0] rOPC; // From decode of aeMB_decode.v
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wire [5:0] rOPC; // From decode of aeMB_decode.v
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wire [31:0] rPC; // From fetch of aeMB_fetch.v
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wire [31:0] rPC; // From fetch of aeMB_fetch.v
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wire [4:0] rRA; // From decode of aeMB_decode.v
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wire [4:0] rRA; // From decode of aeMB_decode.v
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wire [4:0] rRB; // From decode of aeMB_decode.v
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wire [4:0] rRB; // From decode of aeMB_decode.v
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wire [4:0] rRD; // From decode of aeMB_decode.v
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wire [4:0] rRD; // From decode of aeMB_decode.v
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wire [4:0] rRD_; // From decode of aeMB_decode.v
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wire [31:0] rREGA; // From regfile of aeMB_regfile.v
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wire [31:0] rREGA; // From regfile of aeMB_regfile.v
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wire [31:0] rREGB; // From regfile of aeMB_regfile.v
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wire [31:0] rREGB; // From regfile of aeMB_regfile.v
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wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
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wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
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wire rRWE; // From decode of aeMB_decode.v
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wire rRWE; // From decode of aeMB_decode.v
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wire [31:0] rSIMM; // From decode of aeMB_decode.v
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wire [31:0] rSIMM; // From decode of aeMB_decode.v
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wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v
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wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v
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// End of automatics
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// End of automatics
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// INSTANTIATIONS /////////////////////////////////////////////////////////////////
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aeMB_regfile #(DSIZ)
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aeMB_regfile #(DSIZ)
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regfile (/*AUTOINST*/
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regfile (/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_dat_o (dwb_dat_o[31:0]),
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.dwb_dat_o (dwb_dat_o[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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Line 122... |
.rDWBSTB (rDWBSTB),
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.rDWBSTB (rDWBSTB),
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.rDWBWE (rDWBWE),
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.rDWBWE (rDWBWE),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRD_ (rRD_[4:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rFSM (rFSM[1:0]),
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.rFSM (rFSM[1:0]),
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.rPC (rPC[31:0]),
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.rPC (rPC[31:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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Line 138... |
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aeMB_fetch #(ISIZ)
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aeMB_fetch #(ISIZ)
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fetch (/*AUTOINST*/
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fetch (/*AUTOINST*/
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// Outputs
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// Outputs
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.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
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.iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
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.iwb_stb_o (iwb_stb_o),
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.rPC (rPC[31:0]),
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.rPC (rPC[31:0]),
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.rIWBSTB (rIWBSTB),
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// Inputs
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// Inputs
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.nclk (nclk),
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.nclk (nclk),
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.nrst (nrst),
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.nrst (nrst),
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.nrun (nrun),
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.nrun (nrun),
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Line 209... |
.rMXSRC (rMXSRC[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRD_ (rRD_[4:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rDWBSTB (rDWBSTB),
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.rDWBSTB (rDWBSTB),
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.rDWBWE (rDWBWE),
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.rDWBWE (rDWBWE),
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.rIWBSTB (rIWBSTB),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rLNK (rLNK),
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.rLNK (rLNK),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rRWE (rRWE),
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.rRWE (rRWE),
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.rMXLDST (rMXLDST[1:0]),
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.rMXLDST (rMXLDST[1:0]),
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.iwb_stb_o (iwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_we_o (dwb_we_o),
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.dwb_we_o (dwb_we_o),
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// Inputs
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// Inputs
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.sDWBDAT (sDWBDAT[31:0]),
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.sDWBDAT (sDWBDAT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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