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// $Id: aeMB_ctrl.v,v 1.3 2007-11-08 14:17:47 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.4 2007-11-08 17:48:14 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2007/11/08 14:17:47 sybreon
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// Parameterised optional components.
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Changed MSR_IE to disabled at reset as per MB docs.
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// Changed MSR_IE to disabled at reset as per MB docs.
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//
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//
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// Outputs
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// Outputs
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
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dwb_wre_o,
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dwb_wre_o,
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// Inputs
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// Inputs
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rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
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rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
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dwb_ack_i, gclk, grst, gena
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dwb_ack_i, iwb_ack_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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// DATA WISHBONE
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// DATA WISHBONE
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output dwb_stb_o;
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output dwb_stb_o;
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output dwb_wre_o;
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output dwb_wre_o;
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input dwb_ack_i;
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input dwb_ack_i;
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// INST WISHBONE
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input iwb_ack_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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// --- DECODE INSTRUCTIONS
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// --- DECODE INSTRUCTIONS
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// TODO: Simplify
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// TODO: Simplify
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reg [31:2] rPCLNK, xPCLNK;
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reg [31:2] rPCLNK, xPCLNK;
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reg [1:0] rMXDST, xMXDST;
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reg [1:0] rMXDST, xMXDST;
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reg [4:0] rRW, xRW;
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reg [4:0] rRW, xRW;
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wire fSKIP = (rBRA & !rDLY);
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wire fSKIP = (rBRA & !rDLY);
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wire fDACK = !(rDWBSTB ^ dwb_ack_i);
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or rXCE)
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
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if (fSKIP | |rXCE) begin
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if (fSKIP | |rXCE) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xDWBSTB <= 1'h0;
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xDWBSTB <= 1'h0;
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xDWBWRE <= 1'h0;
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xDWBWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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xDWBSTB <= (fLOD | fSTR);
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xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
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xDWBWRE <= fSTR;
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xDWBWRE <= fSTR & iwb_ack_i;
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end
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end
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always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
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always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
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or rRD or rXCE)
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or rRD or rXCE)
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if (fSKIP) begin
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if (fSKIP) begin
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rDWBSTB <= 1'h0;
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rDWBWRE <= 1'h0;
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rMXDST <= 2'h0;
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rMXDST <= 2'h0;
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rRW <= 5'h0;
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rRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else if (gena) begin
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//rPCLNK <= #1 xPCLNK;
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//rPCLNK <= #1 xPCLNK;
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rMXDST <= #1 xMXDST;
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rMXDST <= #1 xMXDST;
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rRW <= #1 xRW;
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rRW <= #1 xRW;
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end
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rDWBSTB <= 1'h0;
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rDWBWRE <= 1'h0;
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// End of automatics
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end else if (fDACK) begin
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rDWBSTB <= #1 xDWBSTB;
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rDWBSTB <= #1 xDWBSTB;
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rDWBWRE <= #1 xDWBWRE;
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rDWBWRE <= #1 xDWBWRE;
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end
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end
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