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// $Id: aeMB_ctrl.v,v 1.4 2007-11-08 17:48:14 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.5 2007-11-09 20:51:52 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2007/11/08 17:48:14 sybreon
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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//
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// Revision 1.3 2007/11/08 14:17:47 sybreon
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// Revision 1.3 2007/11/08 14:17:47 sybreon
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// Parameterised optional components.
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// Parameterised optional components.
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//
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_ctrl (/*AUTOARG*/
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module aeMB_ctrl (/*AUTOARG*/
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// Outputs
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// Outputs
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
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dwb_wre_o,
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dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
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// Inputs
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// Inputs
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rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
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rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
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dwb_ack_i, iwb_ack_i, gclk, grst, gena
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dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [2:0] rMXALU;
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output [2:0] rMXALU;
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output [4:0] rRW;
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output [4:0] rRW;
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output rDWBSTB;
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output rDWBSTB;
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output rFSLSTB;
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input [1:0] rXCE;
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input [1:0] rXCE;
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input rDLY;
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input rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [10:0] rALT;
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input [10:0] rALT;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input dwb_ack_i;
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input dwb_ack_i;
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// INST WISHBONE
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// INST WISHBONE
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input iwb_ack_i;
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input iwb_ack_i;
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// FSL WISHBONE
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output fsl_stb_o;
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output fsl_wre_o;
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input fsl_ack_i;
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// SYSTEM
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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// --- DECODE INSTRUCTIONS
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// --- DECODE INSTRUCTIONS
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// TODO: Simplify
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// TODO: Simplify
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wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
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wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
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wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
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wire fLDST = (&rOPC[5:4]);
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wire fLDST = (&rOPC[5:4]);
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wire fPUT = (rOPC == 6'o33) & rRB[4];
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wire fGET = (rOPC == 6'o33) & !rRB[4];
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// --- OPERAND SELECTOR ---------------------------------
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// --- OPERAND SELECTOR ---------------------------------
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wire fRDWE = |rRW;
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wire fRDWE = |rRW;
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wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
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wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
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(fDIV) ? 3'o6 :
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(fDIV) ? 3'o6 :
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3'o0;
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3'o0;
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end
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end
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// --- RAM CONTROL ---------------------------------------
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reg rDWBSTB, xDWBSTB;
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reg rDWBWRE, xDWBWRE;
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assign dwb_stb_o = rDWBSTB;
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assign dwb_wre_o = rDWBWRE;
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// --- DELAY SLOT REGISTERS ------------------------------
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// --- DELAY SLOT REGISTERS ------------------------------
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reg [31:2] rPCLNK, xPCLNK;
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reg [31:2] rPCLNK, xPCLNK;
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reg [1:0] rMXDST, xMXDST;
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reg [1:0] rMXDST, xMXDST;
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reg [4:0] rRW, xRW;
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reg [4:0] rRW, xRW;
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wire fSKIP = (rBRA & !rDLY);
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wire fSKIP = (rBRA & !rDLY);
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wire fDACK = !(rDWBSTB ^ dwb_ack_i);
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
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always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
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if (fSKIP | |rXCE) begin
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or fSTR or rRD or rXCE)
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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xDWBSTB <= 1'h0;
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xDWBWRE <= 1'h0;
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// End of automatics
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end else begin
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xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
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xDWBWRE <= fSTR & iwb_ack_i;
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end
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always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
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or rRD or rXCE)
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if (fSKIP) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXDST <= 2'h0;
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xMXDST <= 2'h0;
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xRW <= 5'h0;
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xRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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case (rXCE)
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case (rXCE)
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2'o2: xMXDST <= 2'o1;
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2'o2: xMXDST <= 2'o1;
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD) ? 2'o2 :
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(fLOD | fGET) ? 2'o2 :
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(fBRU) ? 2'o1 :
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(fBRU) ? 2'o1 :
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2'o0;
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2'o0;
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endcase
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endcase
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case (rXCE)
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case (rXCE)
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endcase
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endcase
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end // else: !if(fSKIP)
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end // else: !if(fSKIP)
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// --- PIPELINE CONTROL DELAY ----------------------------
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// --- DATA WISHBONE ----------------------------------
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always @(posedge gclk)
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wire fDACK = !(rDWBSTB ^ dwb_ack_i);
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if (grst) begin
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reg rDWBSTB, xDWBSTB;
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reg rDWBWRE, xDWBWRE;
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assign dwb_stb_o = rDWBSTB;
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assign dwb_wre_o = rDWBWRE;
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
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if (fSKIP | |rXCE) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMXDST <= 2'h0;
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xDWBSTB <= 1'h0;
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rRW <= 5'h0;
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xDWBWRE <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (gena) begin
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end else begin
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//rPCLNK <= #1 xPCLNK;
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xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
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rMXDST <= #1 xMXDST;
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xDWBWRE <= fSTR & iwb_ack_i;
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rRW <= #1 xRW;
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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rDWBSTB <= #1 xDWBSTB;
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rDWBSTB <= #1 xDWBSTB;
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rDWBWRE <= #1 xDWBWRE;
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rDWBWRE <= #1 xDWBWRE;
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end
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end
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// --- FSL WISHBONE -----------------------------------
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wire fFACK = !(rFSLSTB ^ fsl_ack_i);
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reg rFSLSTB, xFSLSTB;
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reg rFSLWRE, xFSLWRE;
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assign fsl_stb_o = rFSLSTB;
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assign fsl_wre_o = rFSLWRE;
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always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
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if (fSKIP | |rXCE) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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xFSLSTB <= 1'h0;
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xFSLWRE <= 1'h0;
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// End of automatics
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end else begin
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xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
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xFSLWRE <= fPUT & iwb_ack_i;
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end
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rFSLSTB <= 1'h0;
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rFSLWRE <= 1'h0;
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// End of automatics
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end else if (fFACK) begin
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rFSLSTB <= #1 xFSLSTB;
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rFSLWRE <= #1 xFSLWRE;
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end
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// --- PIPELINE CONTROL DELAY ----------------------------
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rMXDST <= 2'h0;
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rRW <= 5'h0;
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// End of automatics
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end else if (gena) begin
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//rPCLNK <= #1 xPCLNK;
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rMXDST <= #1 xMXDST;
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rRW <= #1 xRW;
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end
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endmodule // aeMB_ctrl
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endmodule // aeMB_ctrl
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No newline at end of file
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No newline at end of file
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