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// $Id: aeMB_ctrl.v,v 1.6 2007-11-10 16:39:38 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.7 2007-11-14 22:14:34 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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//
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.4 2007/11/08 17:48:14 sybreon
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// Revision 1.4 2007/11/08 17:48:14 sybreon
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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module aeMB_ctrl (/*AUTOARG*/
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module aeMB_ctrl (/*AUTOARG*/
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// Outputs
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// Outputs
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
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dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
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dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
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// Inputs
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// Inputs
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rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
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rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
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dwb_ack_i, iwb_ack_i, iwb_dat_i, fsl_ack_i, gclk, grst, gena
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dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [2:0] rMXALU;
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output [2:0] rMXALU;
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output [4:0] rRW;
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output [4:0] rRW;
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output rDWBSTB;
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output rDWBSTB;
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output rFSLSTB;
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output rFSLSTB;
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input [1:0] rXCE;
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//input [1:0] rXCE;
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input rDLY;
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input rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [10:0] rALT;
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input [10:0] rALT;
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input [5:0] rOPC;
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input [5:0] rOPC;
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input [4:0] rRD, rRA, rRB;
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input [4:0] rRD, rRA, rRB;
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input [31:2] rPC;
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input [31:2] rPC;
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input rBRA;
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input rBRA;
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input rMSR_IE;
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input rMSR_IE;
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input [31:0] xIREG;
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// DATA WISHBONE
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// DATA WISHBONE
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output dwb_stb_o;
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output dwb_stb_o;
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output dwb_wre_o;
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output dwb_wre_o;
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input dwb_ack_i;
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input dwb_ack_i;
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// INST WISHBONE
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// INST WISHBONE
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input iwb_ack_i;
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input iwb_ack_i;
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input [31:0] iwb_dat_i;
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// FSL WISHBONE
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// FSL WISHBONE
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output fsl_stb_o;
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output fsl_stb_o;
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output fsl_wre_o;
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output fsl_wre_o;
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input fsl_ack_i;
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input fsl_ack_i;
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wire [5:0] wOPC;
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wire [5:0] wOPC;
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wire [4:0] wRD, wRA, wRB;
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wire [4:0] wRD, wRA, wRB;
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wire [10:0] wALT;
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wire [10:0] wALT;
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assign {wOPC, wRD, wRA, wRB, wALT} = iwb_dat_i; // FIXME: Endian
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assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
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wire fSFT = (rOPC == 6'o44);
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wire fSFT = (rOPC == 6'o44);
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wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
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wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
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wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
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wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
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wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
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wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
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wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
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wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
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wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
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wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
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always @(/*AUTOSENSE*/rBRA or rXCE or wAFWD_M or wAFWD_R or wBCC
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always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
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or wBFWD_M or wBFWD_R or wBRU or wOPC)
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or wBFWD_R or wBRU or wOPC)
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if (rBRA | |rXCE) begin
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//if (rBRA | |rXCE) begin
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if (rBRA) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXALT <= 2'h0;
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xMXALT <= 2'h0;
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xMXSRC <= 2'h0;
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xMXSRC <= 2'h0;
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xMXTGT <= 2'h0;
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xMXTGT <= 2'h0;
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end
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end
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*/
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*/
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reg [2:0] rMXALU, xMXALU;
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reg [2:0] rMXALU, xMXALU;
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always @(/*AUTOSENSE*/rBRA or rXCE or wBRA or wBSF or wDIV or wLOG
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always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
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or wMOV or wMUL or wSFT)
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or wMUL or wSFT)
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if (rBRA | |rXCE) begin
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//if (rBRA | |rXCE) begin
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if (rBRA) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXALU <= 3'h0;
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xMXALU <= 3'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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// --- DELAY SLOT REGISTERS ------------------------------
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// --- DELAY SLOT REGISTERS ------------------------------
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wire fSKIP = (rBRA & !rDLY);
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wire fSKIP = (rBRA & !rDLY);
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always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
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always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
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or fSTR or rRD or rXCE)
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or fSTR or rRD)
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if (fSKIP) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xMXDST <= 2'h0;
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xMXDST <= 2'h0;
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xRW <= 5'h0;
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xRW <= 5'h0;
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// End of automatics
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// End of automatics
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end else begin
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end else begin
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case (rXCE)
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/*
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2'o2: xMXDST <= 2'o1;
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case (rXCE)
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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2'o2: xMXDST <= 2'o1;
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default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD | fGET) ? 2'o2 :
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(fBRU) ? 2'o1 :
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2'o0;
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endcase
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case (rXCE)
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2'o2: xRW <= 5'd14;
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default: xRW <= rRD;
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endcase
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*/
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xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
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(fLOD | fGET) ? 2'o2 :
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(fLOD | fGET) ? 2'o2 :
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(fBRU) ? 2'o1 :
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(fBRU) ? 2'o1 :
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2'o0;
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2'o0;
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endcase
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xRW <= rRD;
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case (rXCE)
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2'o2: xRW <= 5'd14;
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default: xRW <= rRD;
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endcase
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end // else: !if(fSKIP)
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end // else: !if(fSKIP)
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// --- DATA WISHBONE ----------------------------------
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// --- DATA WISHBONE ----------------------------------
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assign dwb_stb_o = rDWBSTB;
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assign dwb_stb_o = rDWBSTB;
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assign dwb_wre_o = rDWBWRE;
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assign dwb_wre_o = rDWBWRE;
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
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always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
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if (fSKIP | |rXCE) begin
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//if (fSKIP | |rXCE) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xDWBSTB <= 1'h0;
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xDWBSTB <= 1'h0;
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xDWBWRE <= 1'h0;
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xDWBWRE <= 1'h0;
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// End of automatics
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// End of automatics
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reg rFSLWRE, xFSLWRE;
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reg rFSLWRE, xFSLWRE;
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assign fsl_stb_o = rFSLSTB;
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assign fsl_stb_o = rFSLSTB;
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assign fsl_wre_o = rFSLWRE;
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assign fsl_wre_o = rFSLWRE;
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always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
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always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
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if (fSKIP | |rXCE) begin
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//if (fSKIP | |rXCE) begin
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if (fSKIP) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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xFSLSTB <= 1'h0;
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xFSLSTB <= 1'h0;
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xFSLWRE <= 1'h0;
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xFSLWRE <= 1'h0;
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// End of automatics
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// End of automatics
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