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// $Id: aeMB_ctrl.v,v 1.7 2007-11-14 22:14:34 sybreon Exp $
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// $Id: aeMB_ctrl.v,v 1.8 2007-11-14 23:19:24 sybreon Exp $
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//
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//
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// AEMB CONTROL UNIT
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// AEMB CONTROL UNIT
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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//
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Revision 1.6 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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// Significant performance optimisations.
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//
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//
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Revision 1.5 2007/11/09 20:51:52 sybreon
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_ctrl (/*AUTOARG*/
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module aeMB_ctrl (/*AUTOARG*/
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// Outputs
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// Outputs
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
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rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
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dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
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fsl_stb_o, fsl_wre_o,
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// Inputs
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// Inputs
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rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
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rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
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dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
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dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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//output [31:2] rPCLNK;
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//output [31:2] rPCLNK;
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output [1:0] rMXDST;
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output [1:0] rMXDST;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [1:0] rMXSRC, rMXTGT, rMXALT;
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output [2:0] rMXALU;
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output [2:0] rMXALU;
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output [4:0] rRW;
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output [4:0] rRW;
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output rDWBSTB;
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//output rDWBSTB;
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output rFSLSTB;
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//output rFSLSTB;
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//input [1:0] rXCE;
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//input [1:0] rXCE;
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input rDLY;
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input rDLY;
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input [15:0] rIMM;
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input [15:0] rIMM;
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input [10:0] rALT;
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input [10:0] rALT;
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