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// $Id: aeMB_edk32.v,v 1.3 2007-11-03 08:34:55 sybreon Exp $
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// $Id: aeMB_edk32.v,v 1.4 2007-11-08 14:17:47 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core
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// AEMB EDK 3.2 Compatible Core
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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// License along with this library; if not, write to the Free Software
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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// USA
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2007/11/03 08:34:55 sybreon
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// Minor code cleanup.
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Changed MSR_IE to disabled at reset as per MB docs.
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// Changed MSR_IE to disabled at reset as per MB docs.
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//
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//
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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// Revision 1.1 2007/11/02 03:25:40 sybreon
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dwb_adr_o,
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dwb_adr_o,
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// Inputs
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
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dwb_ack_i
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dwb_ack_i
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);
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);
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// Bus widths
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parameter IW = 32;
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parameter IW = 32; /// Instruction bus address width
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parameter DW = 32;
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parameter DW = 32; /// Data bus address width
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// Optional functions
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parameter MUL = 1; // Multiplier
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parameter BSF = 1; // Barrel Shifter
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/*AUTOOUTPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
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output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
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output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
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output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To scon of aeMB_scon.v
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input dwb_ack_i; // To scon of aeMB_scon.v, ...
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input iwb_ack_i; // To scon of aeMB_scon.v, ...
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input iwb_ack_i; // To scon of aeMB_scon.v, ...
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
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input sys_clk_i; // To scon of aeMB_scon.v
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input sys_clk_i; // To scon of aeMB_scon.v
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input sys_int_i; // To scon of aeMB_scon.v
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input sys_int_i; // To scon of aeMB_scon.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [1:0] rXCE; // From scon of aeMB_scon.v
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wire [1:0] rXCE; // From scon of aeMB_scon.v
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// End of automatics
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// End of automatics
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wire [31:0] rOPA, rOPB;
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wire [31:0] rRES_MUL, rRES_BSF;
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// --- OPTIONAL COMPONENTS -----------------------------------
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// Trade off hardware size/speed for software speed
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aeMB_mult
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mult (
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// Outputs
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.rRES_MUL (rRES_MUL[31:0]),
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// Inputs
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.rOPA (rOPA[31:0]),
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.rOPB (rOPB[31:0]));
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aeMB_bsft
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bsft (
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// Outputs
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.rRES_BSF (rRES_BSF[31:0]),
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// Inputs
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.rOPA (rOPA[31:0]),
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.rOPB (rOPB[31:0]),
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.rALT (rALT[10:0]));
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// --- NON-OPTIONAL COMPONENTS -------------------------------
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// These components make up the main AEMB processor.
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aeMB_scon
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aeMB_scon
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scon (/*AUTOINST*/
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scon (/*AUTOINST*/
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// Outputs
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// Outputs
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.rXCE (rXCE[1:0]),
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.rXCE (rXCE[1:0]),
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.grst (grst),
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.grst (grst),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rPC (rPC[31:2]),
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.rPC (rPC[31:2]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.dwb_ack_i (dwb_ack_i),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_bpcu #(IW)
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aeMB_bpcu #(IW)
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.dwb_dat_i (dwb_dat_i[31:0]),
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.dwb_dat_i (dwb_dat_i[31:0]),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_xecu #(DW)
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aeMB_xecu #(DW, MUL, BSF)
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xecu (
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xecu (/*AUTOINST*/
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.rOPA (rOPA[31:0]),
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.rOPB (rOPB[31:0]),
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/*AUTOINST*/
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// Outputs
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// Outputs
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.dwb_adr_o (dwb_adr_o[DW-1:2]),
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.dwb_adr_o (dwb_adr_o[DW-1:2]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.dwb_sel_o (dwb_sel_o[3:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rMXALU (rMXALU[2:0]),
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.rMXALU (rMXALU[2:0]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rALT (rALT[10:0]),
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.rSIMM (rSIMM[31:0]),
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.rSIMM (rSIMM[31:0]),
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rPC (rPC[31:2]),
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.rPC (rPC[31:2]),
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.rRES_MUL (rRES_MUL[31:0]),
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.rRES_BSF (rRES_BSF[31:0]),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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