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// $Id: aeMB_edk32.v,v 1.7 2007-11-10 16:39:38 sybreon Exp $
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// $Id: aeMB_edk32.v,v 1.8 2007-11-14 22:14:34 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core
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// AEMB EDK 3.2 Compatible Core
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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//
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// Revision 1.6 2007/11/09 20:51:52 sybreon
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// Revision 1.6 2007/11/09 20:51:52 sybreon
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// Added GET/PUT support through a FSL bus.
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// Added GET/PUT support through a FSL bus.
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//
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//
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// Revision 1.5 2007/11/08 17:48:14 sybreon
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// Revision 1.5 2007/11/08 17:48:14 sybreon
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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// Fixed data WISHBONE arbitration problem (reported by J Lee).
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_edk32 (/*AUTOARG*/
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module aeMB_edk32 (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,
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rFSLSTB, rDWBSTB, iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o,
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dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
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fsl_dat_o, fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_adr_o,
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// Inputs
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// Inputs
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sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
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sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
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fsl_ack_i, dwb_dat_i, dwb_ack_i
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dwb_ack_i, sys_clk_i, sys_rst_i
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);
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);
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// Bus widths
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// Bus widths
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parameter IW = 32; /// Instruction bus address width
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parameter IW = 32; /// Instruction bus address width
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parameter DW = 32; /// Data bus address width
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parameter DW = 32; /// Data bus address width
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output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
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output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
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output fsl_stb_o; // From ctrl of aeMB_ctrl.v
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output fsl_stb_o; // From ctrl of aeMB_ctrl.v
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output fsl_wre_o; // From ctrl of aeMB_ctrl.v
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output fsl_wre_o; // From ctrl of aeMB_ctrl.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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output rDWBSTB; // From ctrl of aeMB_ctrl.v
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output rFSLSTB; // From ctrl of aeMB_ctrl.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To scon of aeMB_scon.v, ...
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input dwb_ack_i; // To ctrl of aeMB_ctrl.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input fsl_ack_i; // To scon of aeMB_scon.v, ...
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input fsl_ack_i; // To ctrl of aeMB_ctrl.v
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input [31:0] fsl_dat_i; // To regf of aeMB_regf.v
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input [31:0] fsl_dat_i; // To regf of aeMB_regf.v
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input iwb_ack_i; // To scon of aeMB_scon.v, ...
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input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v, ...
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input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
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input sys_clk_i; // To scon of aeMB_scon.v
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input sys_int_i; // To ibuf of aeMB_ibuf.v
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input sys_int_i; // To scon of aeMB_scon.v
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input sys_rst_i; // To scon of aeMB_scon.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire gclk; // From scon of aeMB_scon.v
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wire gena; // From scon of aeMB_scon.v
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wire grst; // From scon of aeMB_scon.v
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wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
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wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
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wire [1:0] rATOM; // From bpcu of aeMB_bpcu.v
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wire rBRA; // From bpcu of aeMB_bpcu.v
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wire rBRA; // From bpcu of aeMB_bpcu.v
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wire rDLY; // From bpcu of aeMB_bpcu.v
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wire rDLY; // From bpcu of aeMB_bpcu.v
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wire [31:0] rDWBDI; // From regf of aeMB_regf.v
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wire [31:0] rDWBDI; // From regf of aeMB_regf.v
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wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
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wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
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wire rDWBSTB; // From ctrl of aeMB_ctrl.v
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wire rFSLSTB; // From ctrl of aeMB_ctrl.v
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wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
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wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
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wire rMSR_BIP; // From xecu of aeMB_xecu.v
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wire rMSR_BIP; // From xecu of aeMB_xecu.v
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wire rMSR_IE; // From xecu of aeMB_xecu.v
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wire rMSR_IE; // From xecu of aeMB_xecu.v
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wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
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wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
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wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
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wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGA; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rREGB; // From regf of aeMB_regf.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
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wire [1:0] rXCE; // From scon of aeMB_scon.v
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wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
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// End of automatics
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// End of automatics
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aeMB_scon
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input sys_clk_i;
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scon (/*AUTOINST*/
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input sys_rst_i;
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// Outputs
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.rXCE (rXCE[1:0]),
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wire grst = sys_rst_i;
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.grst (grst),
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wire gclk = sys_clk_i;
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.gclk (gclk),
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
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.gena (gena),
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// Inputs
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.rOPC (rOPC[5:0]),
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.rATOM (rATOM[1:0]),
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.rDWBSTB (rDWBSTB),
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.rFSLSTB (rFSLSTB),
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.dwb_ack_i (dwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.fsl_ack_i (fsl_ack_i),
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.rMSR_IE (rMSR_IE),
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.rMSR_BIP (rMSR_BIP),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.sys_clk_i (sys_clk_i),
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.sys_rst_i (sys_rst_i),
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.sys_int_i (sys_int_i));
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aeMB_ibuf
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aeMB_ibuf
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ibuf (/*AUTOINST*/
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ibuf (/*AUTOINST*/
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// Outputs
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// Outputs
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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Line 133... |
.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rALT (rALT[10:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rSIMM (rSIMM[31:0]),
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.rSIMM (rSIMM[31:0]),
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.xIREG (xIREG[31:0]),
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.iwb_stb_o (iwb_stb_o),
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.iwb_stb_o (iwb_stb_o),
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// Inputs
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// Inputs
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rXCE (rXCE[1:0]),
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.rMSR_IE (rMSR_IE),
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.rMSR_BIP (rMSR_BIP),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.sys_int_i (sys_int_i),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_ctrl
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aeMB_ctrl
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Line 162... |
.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_wre_o (dwb_wre_o),
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.dwb_wre_o (dwb_wre_o),
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.fsl_stb_o (fsl_stb_o),
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.fsl_stb_o (fsl_stb_o),
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.fsl_wre_o (fsl_wre_o),
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.fsl_wre_o (fsl_wre_o),
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// Inputs
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// Inputs
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.rXCE (rXCE[1:0]),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rALT (rALT[10:0]),
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.rALT (rALT[10:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRB (rRB[4:0]),
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.rRB (rRB[4:0]),
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.rPC (rPC[31:2]),
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.rPC (rPC[31:2]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.xIREG (xIREG[31:0]),
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.dwb_ack_i (dwb_ack_i),
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.dwb_ack_i (dwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_ack_i (iwb_ack_i),
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.iwb_dat_i (iwb_dat_i[31:0]),
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.fsl_ack_i (fsl_ack_i),
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.fsl_ack_i (fsl_ack_i),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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Line 188... |
.iwb_adr_o (iwb_adr_o[IW-1:2]),
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.iwb_adr_o (iwb_adr_o[IW-1:2]),
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.rPC (rPC[31:2]),
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.rPC (rPC[31:2]),
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.rPCLNK (rPCLNK[31:2]),
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.rPCLNK (rPCLNK[31:2]),
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.rBRA (rBRA),
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.rBRA (rBRA),
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.rDLY (rDLY),
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.rDLY (rDLY),
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.rATOM (rATOM[1:0]),
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// Inputs
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// Inputs
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.rMXALT (rMXALT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rOPC (rOPC[5:0]),
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.rOPC (rOPC[5:0]),
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.rRD (rRD[4:0]),
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.rRD (rRD[4:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rDWBDI (rDWBDI[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rXCE (rXCE[1:0]),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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aeMB_regf
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aeMB_regf
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Line 237... |
.rRESULT (rRESULT[31:0]),
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.rRESULT (rRESULT[31:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rDWBSEL (rDWBSEL[3:0]),
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.rMSR_IE (rMSR_IE),
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.rMSR_IE (rMSR_IE),
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.rMSR_BIP (rMSR_BIP),
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.rMSR_BIP (rMSR_BIP),
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// Inputs
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// Inputs
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.rXCE (rXCE[1:0]),
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.rREGA (rREGA[31:0]),
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.rREGA (rREGA[31:0]),
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.rREGB (rREGB[31:0]),
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.rREGB (rREGB[31:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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