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// $Id: aeMB_edk32.v,v 1.8 2007-11-14 22:14:34 sybreon Exp $
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// $Id: aeMB_edk32.v,v 1.9 2007-11-14 23:19:24 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core
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// AEMB EDK 3.2 Compatible Core
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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//
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// Revision 1.7 2007/11/10 16:39:38 sybreon
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// Revision 1.7 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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// Significant performance optimisations.
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//
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//
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// Revision 1.6 2007/11/09 20:51:52 sybreon
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// Revision 1.6 2007/11/09 20:51:52 sybreon
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_edk32 (/*AUTOARG*/
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module aeMB_edk32 (/*AUTOARG*/
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// Outputs
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// Outputs
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rFSLSTB, rDWBSTB, iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o,
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iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,
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fsl_dat_o, fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
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dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
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dwb_adr_o,
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// Inputs
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// Inputs
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sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
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sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
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dwb_ack_i, sys_clk_i, sys_rst_i
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dwb_ack_i, sys_clk_i, sys_rst_i
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);
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);
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// Bus widths
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// Bus widths
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output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
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output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
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output fsl_stb_o; // From ctrl of aeMB_ctrl.v
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output fsl_stb_o; // From ctrl of aeMB_ctrl.v
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output fsl_wre_o; // From ctrl of aeMB_ctrl.v
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output fsl_wre_o; // From ctrl of aeMB_ctrl.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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output iwb_stb_o; // From ibuf of aeMB_ibuf.v
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output rDWBSTB; // From ctrl of aeMB_ctrl.v
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output rFSLSTB; // From ctrl of aeMB_ctrl.v
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// End of automatics
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input dwb_ack_i; // To ctrl of aeMB_ctrl.v
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input dwb_ack_i; // To ctrl of aeMB_ctrl.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
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.rMXSRC (rMXSRC[1:0]),
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.rMXSRC (rMXSRC[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXTGT (rMXTGT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rMXALT (rMXALT[1:0]),
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.rMXALU (rMXALU[2:0]),
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.rMXALU (rMXALU[2:0]),
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.rRW (rRW[4:0]),
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.rRW (rRW[4:0]),
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.rDWBSTB (rDWBSTB),
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.rFSLSTB (rFSLSTB),
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.dwb_stb_o (dwb_stb_o),
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.dwb_stb_o (dwb_stb_o),
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.dwb_wre_o (dwb_wre_o),
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.dwb_wre_o (dwb_wre_o),
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.fsl_stb_o (fsl_stb_o),
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.fsl_stb_o (fsl_stb_o),
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.fsl_wre_o (fsl_wre_o),
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.fsl_wre_o (fsl_wre_o),
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// Inputs
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// Inputs
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