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// $Id: aeMB_edk32.v,v 1.10 2007-11-16 21:52:03 sybreon Exp $
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// $Id: aeMB_edk32.v,v 1.11 2007-11-30 17:08:29 sybreon Exp $
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//
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//
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// AEMB EDK 3.2 Compatible Core
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// AEMB EDK 3.2 Compatible Core
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2007/11/16 21:52:03 sybreon
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// Added fsl_tag_o to FSL bus (tag either address or data).
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//
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// Revision 1.9 2007/11/14 23:19:24 sybreon
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// Revision 1.9 2007/11/14 23:19:24 sybreon
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// Fixed minor typo.
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// Fixed minor typo.
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//
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//
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// Revision 1.8 2007/11/14 22:14:34 sybreon
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// Revision 1.8 2007/11/14 22:14:34 sybreon
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// Changed interrupt handling system (reported by M. Ettus).
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// Changed interrupt handling system (reported by M. Ettus).
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wire grst = sys_rst_i;
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wire grst = sys_rst_i;
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wire gclk = sys_clk_i;
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wire gclk = sys_clk_i;
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
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wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
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// --- INSTANTIATIONS -------------------------------------
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aeMB_ibuf
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aeMB_ibuf
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ibuf (/*AUTOINST*/
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ibuf (/*AUTOINST*/
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// Outputs
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// Outputs
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.rIMM (rIMM[15:0]),
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.rIMM (rIMM[15:0]),
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.rRA (rRA[4:0]),
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.rRA (rRA[4:0]),
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.gclk (gclk),
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.gclk (gclk),
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.grst (grst),
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.grst (grst),
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.gena (gena));
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.gena (gena));
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// --- SIMULATION KERNEL ----------------------------------
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// synopsys translate_off
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`ifdef AEMB_SIMULATION_KERNEL
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wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0};
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wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0};
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wire [1:0] wBRA = {rBRA, rDLY};
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wire [3:0] wMSR = {xecu.rMSR_BIP, xecu.rMSR_C, xecu.rMSR_IE, xecu.rMSR_BE};
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always @(posedge gclk) if (gena) begin
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$write ("\n", ($stime/10));
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$writeh (" PC=", iwb_adr );
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$writeh ("\t");
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case (wBRA)
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2'b00: $write(" ");
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2'b01: $write(".");
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2'b10: $write("-");
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2'b11: $write("+");
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endcase // case (wBRA)
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case (rOPC)
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6'o00: if (rRD == 0) $write(" "); else $write("ADD");
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6'o01: $write("RSUB");
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6'o02: $write("ADDC");
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6'o03: $write("RSUBC");
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6'o04: $write("ADDK");
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6'o05: case (rIMM[1:0])
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2'o0: $write("RSUBK");
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2'o1: $write("CMP");
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2'o3: $write("CMPU");
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default: $write("XXX");
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endcase // case (rIMM[1:0])
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6'o06: $write("ADDKC");
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6'o07: $write("RSUBKC");
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6'o10: $write("ADDI");
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6'o11: $write("RSUBI");
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6'o12: $write("ADDIC");
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6'o13: $write("RSUBIC");
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6'o14: $write("ADDIK");
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6'o15: $write("RSUBIK");
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6'o16: $write("ADDIKC");
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6'o17: $write("RSUBIKC");
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6'o20: $write("MUL");
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6'o21: case (rALT[10:9])
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2'o0: $write("BSRL");
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2'o1: $write("BSRA");
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2'o2: $write("BSLL");
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default: $write("XXX");
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endcase // case (rALT[10:9])
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6'o22: $write("IDIV");
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6'o30: $write("MULI");
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6'o31: case (rALT[10:9])
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2'o0: $write("BSRLI");
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2'o1: $write("BSRAI");
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2'o2: $write("BSLLI");
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default: $write("XXX");
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endcase // case (rALT[10:9])
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6'o33: case (rRB[4:2])
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3'o0: $write("GET");
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3'o4: $write("PUT");
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3'o2: $write("NGET");
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3'o6: $write("NPUT");
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3'o1: $write("CGET");
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3'o5: $write("CPUT");
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3'o3: $write("NCGET");
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3'o7: $write("NCPUT");
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endcase // case (rRB[4:2])
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6'o40: $write("OR");
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6'o41: $write("AND");
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6'o42: if (rRD == 0) $write(" "); else $write("XOR");
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6'o43: $write("ANDN");
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6'o44: case (rIMM[6:5])
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2'o0: $write("SRA");
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2'o1: $write("SRC");
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2'o2: $write("SRL");
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2'o3: if (rIMM[0]) $write("SEXT16"); else $write("SEXT8");
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endcase // case (rIMM[6:5])
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6'o45: $write("MOV");
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6'o46: case (rRA[3:2])
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3'o0: $write("BR");
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3'o1: $write("BRL");
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3'o2: $write("BRA");
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3'o3: $write("BRAL");
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endcase // case (rRA[3:2])
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6'o47: case (rRD[2:0])
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3'o0: $write("BEQ");
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3'o1: $write("BNE");
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3'o2: $write("BLT");
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3'o3: $write("BLE");
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3'o4: $write("BGT");
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3'o5: $write("BGE");
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default: $write("XXX");
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endcase // case (rRD[2:0])
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6'o50: $write("ORI");
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6'o51: $write("ANDI");
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6'o52: $write("XORI");
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6'o53: $write("ANDNI");
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6'o54: $write("IMMI");
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6'o55: case (rRD[1:0])
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2'o0: $write("RTSD");
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2'o1: $write("RTID");
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2'o2: $write("RTBD");
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default: $write("XXX");
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endcase // case (rRD[1:0])
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6'o56: case (rRA[3:2])
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3'o0: $write("BRI");
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3'o1: $write("BRLI");
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3'o2: $write("BRAI");
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3'o3: $write("BRALI");
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endcase // case (rRA[3:2])
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6'o57: case (rRD[2:0])
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3'o0: $write("BEQI");
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3'o1: $write("BNEI");
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3'o2: $write("BLTI");
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3'o3: $write("BLEI");
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3'o4: $write("BGTI");
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3'o5: $write("BGEI");
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default: $write("XXX");
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endcase // case (rRD[2:0])
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6'o60: $write("LBU");
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6'o61: $write("LHU");
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6'o62: $write("LW");
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6'o64: $write("SB");
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6'o65: $write("SH");
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6'o66: $write("SW");
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6'o70: $write("LBUI");
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6'o71: $write("LHUI");
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6'o72: $write("LWI");
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6'o74: $write("SBI");
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6'o75: $write("SHI");
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6'o76: $write("SWI");
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default: $write("XXX");
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endcase // case (rOPC)
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case (rOPC[3])
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1'b1: $writeh("\tr",rRD,", r",rRA,", h",rIMM);
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1'b0: $writeh("\tr",rRD,", r",rRA,", r",rRB," ");
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endcase // case (rOPC[3])
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// ALU
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$write("\t");
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$writeh(" A=",xecu.rOPA);
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$writeh(" B=",xecu.rOPB);
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case (rMXALU)
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3'o0: $write(" ADD");
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3'o1: $write(" LOG");
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3'o2: $write(" SFT");
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3'o3: $write(" MOV");
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3'o4: $write(" MUL");
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3'o5: $write(" BSF");
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default: $write(" XXX");
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endcase // case (rMXALU)
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$writeh("=h",xecu.xRESULT);
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// WRITEBACK
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$writeh("\tSR=", wMSR," ");
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if (regf.fRDWE) begin
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case (rMXDST)
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2'o2: begin
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if (dwb_stb_o) $writeh("R",rRW,"=RAM(h",regf.xWDAT,")");
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if (fsl_stb_o) $writeh("R",rRW,"=FSL(h",regf.xWDAT,")");
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end
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2'o1: $writeh("R",rRW,"=LNK(h",regf.xWDAT,")");
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2'o0: $writeh("R",rRW,"=ALU(h",regf.xWDAT,")");
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endcase // case (rMXDST)
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end
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// STORE
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if (dwb_stb_o & dwb_wre_o) begin
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$writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
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case (dwb_sel_o)
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4'hF: $write(":L");
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4'h3,4'hC: $write(":W");
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4'h1,4'h2,4'h4,4'h8: $write(":B");
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endcase // case (dwb_sel_o)
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end
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end // if (gena)
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`endif // `ifdef AEMB_SIMULATION_KERNEL
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// synopsys translate_on
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endmodule // aeMB_edk32
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endmodule // aeMB_edk32
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No newline at end of file
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No newline at end of file
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