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[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] [aeMB_ibuf.v] - Diff between revs 41 and 44

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// $Id: aeMB_ibuf.v,v 1.1 2007-11-02 03:25:40 sybreon Exp $
// $Id: aeMB_ibuf.v,v 1.2 2007-11-02 19:20:58 sybreon Exp $
//
//
// AEMB INSTRUCTION BUFFER
// AEMB INSTRUCTION BUFFER
// 
// 
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
//  
//  
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// License along with this library; if not, write to the Free Software
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
// USA
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2007/11/02 03:25:40  sybreon
 
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
 
// Fixed various minor data hazard bugs.
 
// Code compatible with -O0/1/2/3/s generated code.
 
//
 
 
module aeMB_ibuf (/*AUTOARG*/
module aeMB_ibuf (/*AUTOARG*/
   // Outputs
   // Outputs
   rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
   rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
   // Inputs
   // Inputs
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   // TODO: Assign to FIFO not full.
   // TODO: Assign to FIFO not full.
   assign       iwb_stb_o = 1'b1;
   assign       iwb_stb_o = 1'b1;
 
 
   reg [31:0]    rSIMM, xSIMM;
   reg [31:0]    rSIMM, xSIMM;
   wire [31:0]   wSIMM = (fIMM) ? {rIMM, wIDAT[15:0]} : { {(16){wIDAT[15]}}, wIDAT[15:0]}; // TODO: Factor
 
   wire         fIMM = (rOPC == 6'o54);
   wire         fIMM = (rOPC == 6'o54);
 
 
   reg [31:0]    xIREG;
   reg [31:0]    xIREG;
 
 
   // DELAY SLOT
   // DELAY SLOT
   always @(/*AUTOSENSE*/rBRA or wIDAT)
   always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or rXCE or wIDAT) begin
     if (rBRA) begin
      xIREG <= (rBRA | |rXCE) ? 32'h88000000 : wIDAT;
        xIREG <= 32'h88000000;
      xSIMM <= (fIMM) ? {rIMM, wIDAT[15:0]} : { {(16){wIDAT[15]}}, wIDAT[15:0]};
        /*AUTORESET*/
 
     end else begin
 
        xIREG <= wIDAT; // FIXME: Simplify
 
        //xSIMM <= wSIMM;
 
     end
 
 
 
   always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or xIREG)
 
     if (rBRA) begin
 
        /*AUTORESET*/
 
        // Beginning of autoreset for uninitialized flops
 
        xSIMM <= 32'h0;
 
        // End of automatics
 
     end else begin
 
        //xIREG <= wIDAT; // FIXME: Simplify
 
        xSIMM <= (fIMM) ? {rIMM, xIREG[15:0]} : { {(16){xIREG[15]}}, xIREG[15:0]}; // TODO: Factor
 
     end
     end
 
 
   // Synchronous
   // Synchronous
   always @(posedge gclk)
   always @(posedge gclk)
     if (grst) begin
     if (grst) begin

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