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// $Id: aeMB_ibuf.v,v 1.4 2007-11-10 16:39:38 sybreon Exp $
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// $Id: aeMB_ibuf.v,v 1.5 2007-11-14 22:14:34 sybreon Exp $
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//
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//
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// AEMB INSTRUCTION BUFFER
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// AEMB INSTRUCTION BUFFER
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//
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//
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//
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//
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//
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//
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// You should have received a copy of the GNU Lesser General Public
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// You should have received a copy of the GNU Lesser General Public
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2007/11/10 16:39:38 sybreon
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// Upgraded license to LGPLv3.
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// Significant performance optimisations.
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//
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// Revision 1.3 2007/11/03 08:34:55 sybreon
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// Revision 1.3 2007/11/03 08:34:55 sybreon
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// Minor code cleanup.
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// Minor code cleanup.
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//
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//
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Revision 1.2 2007/11/02 19:20:58 sybreon
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// Added better (beta) interrupt support.
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// Added better (beta) interrupt support.
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// Code compatible with -O0/1/2/3/s generated code.
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// Code compatible with -O0/1/2/3/s generated code.
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//
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//
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module aeMB_ibuf (/*AUTOARG*/
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module aeMB_ibuf (/*AUTOARG*/
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// Outputs
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// Outputs
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
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rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, iwb_stb_o,
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// Inputs
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// Inputs
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rBRA, rXCE, iwb_dat_i, iwb_ack_i, gclk, grst, gena
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rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
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grst, gena
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);
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);
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// INTERNAL
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// INTERNAL
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output [15:0] rIMM;
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output [15:0] rIMM;
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output [4:0] rRA, rRD, rRB;
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output [4:0] rRA, rRD, rRB;
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output [10:0] rALT;
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output [10:0] rALT;
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output [5:0] rOPC;
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output [5:0] rOPC;
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output [31:0] rSIMM;
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output [31:0] rSIMM;
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output [31:0] xIREG;
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input rBRA;
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input rBRA;
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input [1:0] rXCE;
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//input [1:0] rXCE;
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input rMSR_IE;
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input rMSR_BIP;
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// INST WISHBONE
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// INST WISHBONE
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output iwb_stb_o;
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output iwb_stb_o;
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input [31:0] iwb_dat_i;
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input [31:0] iwb_dat_i;
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input iwb_ack_i;
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input iwb_ack_i;
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// SYSTEM
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// SYSTEM
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input sys_int_i;
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// SYSTEM
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input gclk, grst, gena;
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input gclk, grst, gena;
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reg [15:0] rIMM;
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reg [15:0] rIMM;
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reg [4:0] rRA, rRD;
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reg [4:0] rRA, rRD;
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reg [5:0] rOPC;
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reg [5:0] rOPC;
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// TODO: Assign to FIFO not full.
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// TODO: Assign to FIFO not full.
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assign iwb_stb_o = 1'b1;
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assign iwb_stb_o = 1'b1;
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reg [31:0] rSIMM, xSIMM;
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reg [31:0] rSIMM, xSIMM;
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wire fIMM = (rOPC == 6'o54);
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wire [31:0] wXCEOP = 32'hB9CE0008;
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wire [31:0] wINTOP = 32'hB9CE0010;
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wire [31:0] wBRKOP = 32'hB9CE0018;
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wire [31:0] wBRAOP = 32'h88000000;
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wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
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reg [31:0] xIREG;
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reg [31:0] xIREG;
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// DELAY SLOT
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or rXCE or wIDAT) begin
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// --- INTERRUPT LATCH --------------------------------------
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xIREG <= (rBRA | |rXCE) ? 32'h88000000 : wIDAT;
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// Debounce and latch onto the positive edge. This is independent
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xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} : {rIMM, wIDAT[15:0]};
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// of the pipeline so that stalls do not affect it.
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reg rFINT;
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reg [1:0] rDINT;
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//wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i;
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wire wSHOT = !rDINT[0] & sys_int_i;
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rDINT <= 2'h0;
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rFINT <= 1'h0;
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// End of automatics
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end else if (rMSR_IE) begin
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rDINT <= #1 {rDINT[0], sys_int_i};
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rFINT <= (wIREG == wINTOP) ? 1'b0 : (rFINT | wSHOT);
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end
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wire fIMM = (rOPC == 6'o54);
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wire fRTD = (rOPC == 6'o55);
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wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
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wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));
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// --- DELAY SLOT -------------------------------------------
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always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
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or wBRAOP or wIDAT or wINTOP) begin
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xIREG <= (rBRA) ? wBRAOP :
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(!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
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wIDAT;
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end
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always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
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//xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} : {rIMM, wIDAT[15:0]};
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xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
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{rIMM, wIDAT[15:0]};
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end
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end
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// Synchronous
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// --- PIPELINE --------------------------------------------
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rIMM <= 16'h0;
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rIMM <= 16'h0;
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